Multi-Channel HDLC Controller Based on FPGA

Fan Gong Gong; Qiang Wu; Tong Yin; Qing Shan Liu

doi:10.4028/www.scientific.net/AMR.718-720.1365

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 718-720Multi-Channel HDLC Controller Based on FPGA

Multi-Channel HDLC Controller Based on FPGA

Abstract:

The common method of implementing a HDLC controller is either using an ASIC device or designing it with software. It is easy to implement a HDLC controller with an ASIC device, but it is hard to modify it. The software method introduces a flexible way, but it will occupy a huge amount of CPU resource, and the timing parameters are hard to ensure. Designing HDLC controller with FPGA can take advantage of both speed and flexibility, furthermore, with the programmable ability of FPGA, more than one channel can be implemented in a single FPGA. This paper introduces a HDLC controller design base on Alteras Cyclone III FPGA and Quartus II developing environment. The controller contains four HDLC channels and an interface for PC104 bus. Except the basic HDLC protocol, more functions are added into the controller, such as alterable flag sequence, built-in timer and so on. The design has been fully tested, and has been used in a communication production successfully.

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Periodical:

Advanced Materials Research (Volumes 718-720)

Pages:

1365-1370

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.718-720.1365

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Online since:

July 2013

Authors:

Fan Gong Gong, Qiang Wu, Tong Yin, Qing Shan Liu

Keywords:

CRC, Field-Programmable Gate Array (FPGA), HDLC, Multi-Channel, PC104

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References

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