A 1V 2.52-kS/s 367nW Rail-to-Rail 10-Bit Successive Approximation ADC

Abstract:

A 10-bit successive approximation (SAR) analog-to-digital converter (ADC) in 90nm CMOS dedicated for sample rate limited applications is presented. The SAR ADC achieves an extra low energy by applying only one pre-opamp and without any low voltage techs in preserving the desired low power. HSPICE simulation results show that at a supply voltage of 1V and an output rate of 2.52kS/s, the SAR ADC performs a peak signal-to-noise-and-distortion ratio of 56.8dB. Our SAR ADC consumes 367nW in the simulation, corresponding to a figure of merits of 258.1fJ/conversion-step. And at lowest sample rate mode with an output rate of 126S/s, the ADC consumes only 21nW.

• Periodical: Advanced Materials Research (Volumes 718-720)
• Pages: 1717-1722
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.718-720.1717
• Online since: July 2013
• Authors: Xiao Yang Huang, Liu Lei Zhou, Wen Shi Li
• Keywords: Low Supply Voltage, One Pre-Opamp, Sample Rate Limitation, Successive Approximation, Switched-Capacitor Circuit

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