A High Speed Open-Loop Track/Hold Circuit in CMOS Process

Zheng Ping Zhang; Yong Lu Wang; Ming Liu

doi:10.4028/www.scientific.net/AMR.756-759.4302

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 756-759A High Speed Open-Loop Track/Hold Circuit in CMOS...

A High Speed Open-Loop Track/Hold Circuit in CMOS Process

Abstract:

A high speed open-loop track/hold circuit in 0.18um CMOS process is presented. Open-loop and differential architecture are adopted to obtain high bandwidth and high speed;time-interleaved structure is used to reach a high sampling rate;source negative feedback and offset compensation are used to improve the linearity of the circuit.Simulation results show that with 396.875MHz input, 1.6GSPS sampling rate, driving the pre-amplifier of ADC, the thack/hold circuits SFDR(spurious-free dynamic range) is 75.8dB,satisfying the demand of 12 bits ADC.The circuit features high sampling rate,wide bandwidth,high SFDR and universal.

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Periodical:

Advanced Materials Research (Volumes 756-759)

Pages:

4302-4305

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.756-759.4302

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Online since:

September 2013

Authors:

Zheng Ping Zhang, Yong Lu Wang, Ming Liu

Keywords:

High Bandwidth, High-Speed, Time-Interleaved, Track/Hold

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