Design of Vehicle CAN-Network Bit-Level Interference Testing System Based on FPGA

An Yu Cheng; Ju Lin Zhang; Gang Wang

doi:10.4028/www.scientific.net/AMR.765-767.129

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 765-767Design of Vehicle CAN-Network Bit-Level...

Design of Vehicle CAN-Network Bit-Level Interference Testing System Based on FPGA

Abstract:

In order to ensure the system behavior of vehicle CAN network and its ECU nodes meet the requirements of high fault tolerance in complex communication conditions. The CAN networks bit-level interference test method in data link layer based on FPGA was studied. Monitored bit stream and embedded interference by behavior level description through Verilog HDL based on FPGA. Simultaneously, host computer configuration interface which is based on Visual C++ was developed. Using the design of this paper interfered the CAN network evidenced the design can implement interference effectively and flexibly to CAN, reliable stability and high fault tolerance of CAN network can be verified.

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Periodical:

Advanced Materials Research (Volumes 765-767)

Pages:

129-133

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.765-767.129

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Online since:

September 2013

Authors:

An Yu Cheng, Ju Lin Zhang, Gang Wang

Keywords:

Controller Area Network (CAN), Interference Test, Network Performance, System on Chip (SoC)

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