Implementation of Decoder for Effective Quasi-Cyclic LDPC Codes Based on FPGA

Ji Qu Han; Li Liu

doi:10.4028/www.scientific.net/AMR.791-793.1867

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 791-793Implementation of Decoder for Effective...

Implementation of Decoder for Effective Quasi-Cyclic LDPC Codes Based on FPGA

Abstract:

Designers are increasingly relying on FPGA-based emulation to evaluate the performance of LDPC codes. In this paper, we propose a novel approximate lower triangular structure for the parity part of the parity-check matrix of QC-LDPC codes. Next, a high speed partially parallel decoder architecture which based on the Offset BP-based decoding algorithm is proposed. The results indicate that the frequency can reach 100MHz and its throughput rate can reach 113Mbps.

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Periodical:

Advanced Materials Research (Volumes 791-793)

Pages:

1867-1871

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.791-793.1867

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Online since:

September 2013

Authors:

Ji Qu Han, Li Liu

Keywords:

Approximate Lower Triangular Structure, Field-Programmable Gate Array (FPGA), Low-Density Parity-Check (LDPC), Offset BP-Based Decoding Algorithm

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References

[1] R. Gallager, Low-density parity-check codes, IEEE Trans. Inf. Theory , vol. IT-8, no. 1, p.21–28, Jan. (1962).

DOI: 10.1109/tit.1962.1057683

Google Scholar

[2] J. Lin, Z. Wang, L. Li, J. Sha, and M. Gao, Efficient shuffle network ar-chitecture and application for WiMAX LDPC decoders, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 3, p.215–219, Mar. (2009).

DOI: 10.1109/tcsii.2009.2015353

Google Scholar

[3] Xiaoheng Chen, Jingyu Kang, Shu Lin, Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders, IEEE Trans. on circuits and systems-I: regular papers, vol. 58, No. 1, january (2011).

DOI: 10.1109/tcsi.2010.2055250

Google Scholar

[4] S. Lin and D. J. Costello, Jr, Error Control Coding: Fundamentals and Applications, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, (2004).

Google Scholar

[5] Wai M. Tam, Francis C. M. Lau. A Class of QC-LDPC Codes with Low Encoding Complexity and Good Error Performance[J]. IEEE Communication Letters, 2010, 14(2): 169-171.

DOI: 10.1109/lcomm.2010.02.091930

Google Scholar

[6] Richardson.T. J, Uranke.R. L, The Capacity of Low-Density Parity-Check codes under message-passing Decoding, IEEE Trans on Inform Theory, 200 1, 47(2), PP. 599-618.

DOI: 10.1109/18.910577

Google Scholar

[7] M. Fossorier, M. Mihaljevic, and H. Imai, Reduced complexity itera-tive decoding of low-density parity check codes based on belief propa-gation, IEEE Trans. Commun. , vol. 47, no. 5, p.673–680, May (1999).

DOI: 10.1109/26.768759

Google Scholar