ESD and LU Immunities of LV nMOSFETs by the Drain-Contact Variations

Abstract:

The non-uniform turned-on issue of a multi-finger GGnMOS is deeply affect the ESD robustness. This paper introduces a drain-side engineering: by removing the drain contacts to increase the R_on value of a GGnMOS. However, after the actual systematic testing, it can be concluded that removing the drain contacts will obviously decrease the ESD capability and this way is not good for the ESD ability. The I_t2 value in the Type-1.1 DUT becomes only 56% of the reference group (Ref. DUT). The I_t2 value will increase as along with the contact number to increase. Meanwhile, the layout pattern of the contacts concentrated around the both ends will have a higher I_t2 value, i.e., (I_t2)_type2 > (I_t2)_type1, the increasing percentage of I_t2 values of Type-2 as compared with Type-1 can be up to 8.63%. So, a drain-contact arrangement will strongly affect the device ESD ability.

• Periodical: Advanced Materials Research (Volumes 798-799)
• Pages: 608-613
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.798-799.608
• Online since: September 2013
• Authors: Shen Li Chen, Min Hua Lee
• Keywords: Electrostatic Discharge (ESD), GGnMOS, Holding Voltage (V_h), Latch-Up (LU), Multi-Finger Layout, Non-Uniform Turned on, Secondary Breakdown Current (I_t2), Transmission Line Pulse (TLP), Trigger Voltage (V_t1)

References

[1] Ming-Dou Ker, Tung-Yang Chen, Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit, Journal of Electrostatics 54 (2002), 73-93.

DOI: 10.1016/s0304-3886(01)00154-1

[2] Christian Russ, ESD issues in advanced CMOS bulk and FinFET technologies: Processing, protection devices and circuit strategies, Microelectronics Reliability 48 (2008), 1403-1411.

DOI: 10.1016/j.microrel.2008.07.042

[3] Yong-Seo Koo, Kwang-Yeob Lee, Joong-Ho Choi, Chan-Ho Lee, Yoon-Sik Lee, Yil-Suk Yang, Electrical characteristics of novel ESD protection devices for I/O and power clamp, IEEE International Symposium on Circuits and Systems (2011), 937-940.

DOI: 10.1109/icm.2010.5696214

[4] Peng Zhang, Yuan Wang, Song Jia, Xing Zhang, Analysis of the influence of contact position to the ESD protection ability in GGnmos device, Lecture Notes in Electrical Engineering 134 (2011), 273-278.

DOI: 10.1007/978-3-642-25905-0_36

[5] Fei Ma, Yan Han, Bo Song, Shurong Dong, Meng Miao, Jianfeng Zheng, Jian Wu, Kehan Zhu, Substrate-engineered GGNMOS for low trigger voltage ESD in 65nm CMOS process, Microelectronics Reliability 51 (2011), 2124-2128.

DOI: 10.1016/j.microrel.2011.07.028

[6] Li Li, Hongxia Liu, Zhaonian Yang, Linlin Chen, A novel co-design and evaluation methodology for ESD protection in RF IC, Microelectronics Reliability 52 (2012), 2632-2639.

DOI: 10.1016/j.microrel.2012.06.003

[7] Ming-Dou Ker, Che-Hao Lo, Wen-Yu Chuang, Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0. 18-μm salicided CMOS process, 8th IEEE International Conference on Electronics, Circuits and Systems (2001), 361-364.

DOI: 10.1109/icecs.2001.957754

[8] Ming-Dou Ker and Jia-Huei Chen, Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices, IEEE Journal of Solid-State Circuits 41 (2006), 2601-2609.

DOI: 10.1109/jssc.2006.883331

[9] François Dieudonné, Aurore Constant, Benoit Gautheron, Jean-François Revel, New method for non destructive snap-back characterization in multi-finger power MOSFETs, IEEE Conference on Microelectronic Test Structures (2008), 137-141.

DOI: 10.1109/icmts.2008.4509328

[10] Mingu Kang, Ilgu Yun, Modeling electrical characteristics for multi-finger MOSFETs based on drain voltage variation, Transactions on Electrical and Electronic Materials (2011), 245-248.

DOI: 10.4313/teem.2011.12.6.245

[11] Shen-Li Chen and Min-Hua Lee, Layout Strategy of P+ Pick-up on the LV MOST ESD Reliability in 0. 6mm to 0. 18mm CMOS Processes, International Symposium on Next-Generation Electronics (2013), 51-54.

DOI: 10.1109/isne.2013.6512283

[12] Shen-Li Chen and Guan-Jhong Chen, Evaluating nMOSFET ESD Protection Designs: An Overview, Journal of Applied Mechanics and Materials 268 (2013), 1357-1360.

DOI: 10.4028/www.scientific.net/amm.268-270.1357