The Results of Self-Annealing Process for a Copper Interconnection on the 4xnm DRAM Products

Abstract:

In DRAM products, the copper interconnections with larger grain size are preferred for lower electrical resistance and better circuit performance. We studied the copper properties which are the evolution of the grain size, distribution of the grain, and the metal line texture formation during self-annealing. And we were able to evaluate the thermal budget in the DRAM process by performing thermal excursion stress test. We found out that the condition with self-annealing time affects copper grain size and stress migration. It has been measured by the EBSD analysis system and TOF-TEM. Compared with the conventional copper anneal process which has no time delay, the self-annealing process with time delay showed the more bamboo microstructure at dram damascene process. In addition, we observed that the self-annealing process helped enhanced thermal stress stability, which is caused by lower hillock deformation to copper top surface after a batch furnace at 400°C, N2 ambient for three times.

• Periodical: Advanced Materials Research (Volumes 816-817)
• Pages: 101-105
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.816-817.101
• Online since: September 2013
• Authors: Hyung Jin Park, In Cheol Ryu, Young Pyo Song, Hong Shin Jun, Kun Sang Yoon
• Keywords: EBSD, Electro Plating Copper, Grain Growth, Self-Anneal

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