Influence of Lithography Distortion due to Metal Fill on CA

Abstract:

In the process of integrated circuit design and manufacturing, dummy metal fill can improve the planarity of layout after Chemical Mechanical Polishing (CMP). However, it will also cause lithography distortion and Critical Area (CA) variation. This paper compares and analyzes the influences of lithography distortion due to metal fill on CA from the perspectives of different defect particles based on 45nm technology node. The results indicate that dummy metal fill can increase open CA after lithography and the defect particle with the diameter of 0.066um leads to the largest increment percentage of open CA, which will take up almost 10%. This paper is instructive in researching dummy metal fill and CA or related fields in the future.

• Periodical: Advanced Materials Research (Volume 900)
• Pages: 651-655
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.900.651
• Online since: February 2014
• Authors: Xiao Ming Chen, Ke Qin Wang, Song Song Li
• Keywords: Critical Area, DFM, Lithography, Metal Fill

References

[1] A. B. Kahng and K. Samadi, CMP fill synthesis: A survey of recent studies, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, pp.3-19, (2008).

DOI: 10.1109/tcad.2007.907061

[2] Y. Cheng, Design For Manufacturing (DFM) in Nano-CMOS era, in Nanoelectronics Conference, 2008. INEC 2008. 2nd IEEE International, 2008, pp.524-529.

DOI: 10.1109/inec.2008.4585541

[3] A. Kurokawa, T. Kanamoto, T. Ibe, A. Kasebe, C. W. Fong, T. Kage, Y. Inoue, and H. Masuda, Dummy filling methods for reducing interconnect capacitance and number of fills, in Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, 2005, pp.586-591.

DOI: 10.1109/isqed.2005.47

[4] V. B. Suresh, P. V. Kumar, and S. Kundu, On lithography aware metal-fill insertion, Proceedings 2012 13th International Symposium on Quality Electronic Design (ISQED 2012), pp.200-7, 2012 (2012).

DOI: 10.1109/isqed.2012.6187495

[5] N. Dhumane, S. Kundu, and Ieee, Critical Area Driven Dummy Fill Insertion to Improve Manufacturing Yield, in 2012 13th International Symposium on Quality Electronic Design, ed New York: Ieee, 2012, pp.334-341.

DOI: 10.1109/isqed.2012.6187514

[6] A. Sreedhar, S. Kundu, and Ieee, On Linewidth-based Yield Analysis for Nanometer Lithography, in Date: 2009 Design, Automation & Test in Europe Conference & Exhibition, Vols 1-3, ed, 2009, pp.381-386.

DOI: 10.1109/date.2009.5090693

[7] T. -B. Chan, R. S. Ghaida, and P. Gupta, Electrical modeling of lithographic imperfections, " in VLSI Design, 2010. VLSID, 10. 23rd International Conference on, 2010, pp.423-428.

DOI: 10.1109/vlsi.design.2010.24