Advanced Materials Research Vols. 931-932

Abstract: This paper presents an interleaved double dual boost converter (IDDB) used in renewable energy application where high voltage gain is required such as fuel cell or photovoltaic applications, etc. Two types of controllers are applied to this converter, 1) a controller based on Flatness properties for regulating the output voltage (outer loop); 2) a sliding mode controller for inductor current (inner loop). The variation of the input voltage is compensated by trajectory planning process. The validation of the proposed system is done through experimental results.

Abstract: This paper presents an interleaved double dual boost converter used in renewable energy application, for example, photovoltaic cell. The converter is interesting because its high voltage gain property. Its operating functions in the possible cases are detailed. Moreover, the presence of negative current in a certain operating point is investigated. The validation of the proposed system is done through experimental results.

Abstract: In this paper, we propose a flash type A/D (Analog-to-Digital) converter. This circuit uses a neuron CMOS inverter as a judgement component of the voltage level. It is smaller than traditional analog comparators in the power consumption and the layout area. Therefore, the power consumption and the layout area of this circuit can be reduced further compared with the conventional A/D converter using the analog comparator. Furthermore, we could confirm that the proposed circuit has a characteristic of high-speed operation.

Abstract: For energy-harvesting systems utilizing thermoelectric energy, a dual Fibonacci converter using power saving techniques is proposed. Compared with conventional converters, the proposed converter can provide higher output voltages without magnetic components. The output voltage of the proposed converter is expressed by the k-step (2, 3, 4 ...) Fibonacci numbers. Furthermore, a novel control technique is proposed to utilize the energy stored in stray parasitic capacitances effectively. The result of simulation program with integrated circuit emphasis (SPICE) simulations shows that the proposed converter can provide higher output voltages than conventional converters. Furthermore, more than 8.4% of power efficiency is improved by the proposed technique.

Abstract: This paper presents all current-mode operate in high precision vector summation circuit used CMOS technology 0.5 um level 3. The structure of the circuit consists of two parts: a squared and current mirror circuit. This is designed to work in all current modes which relies equations, quadratic functions. Make use fewer transistors, makes it easy to understand, but the number of transistors with high fidelity and distortion of the signal. The simulation of the circuit relies on the CMOS during saturation. With input sinusoidal input signal displayed by using the PSpice circuit analysis.

Abstract: In digital communications, since it is of importance that the receiving data is identical to the transmitted data, the error correcting code is one good solution to maintaining the information accuracy between the transmitter and the receiver. This research paper proposes the application of the error correcting code to Wireless Body Area Network (WBAN). The error correcting code in this research work is the concatenate code of the Reed-Solomon code (RS) and the convolutional code (CC). Information data in WBAN with the Rician channel condition is modulated with the Binary Phase Shift Keying (BPSK) scheme. In addition, the path loss of WBAN is examined. The Additive White Gaussian Noise (AWGN) and Rayleigh fading channels are employed for comparison purposes to illustrate the effects on bit error performance of different channel environments. The RS code is an outer code while the convolutional code an inner code. The findings show that the concatenate code performs better than the single codes, i.e. RS and CC. At BER 10^-3, the concatenate code {RS(255,223)+CC(171,133)} is better than either RS(255,223) at 5dB or CC(171,133) at 1.5dB. If the inner code is changed to CC(7,5) at BER 10^-3, the performance is reduced by approximately 0.6dB. Thus, the coding complexity can be tailored according to the desired error correcting capability.

Abstract: This paper proposed low cost instruments for wireless communication based on LabVIEW program. Conventional monitoring and controlling method using LabVIEW need several unique devices including data acquisition card (DAQ), RS232, wireless data acquisition (WDA), the serial and parallel interfaces which lead to expensive cost and complex system. This paper explains the new design of wireless interface devices which uses Wi-Fi USB, MCU board, and RS232 using LabVIEW to save cost. The objective is to develop low cost and easy tools for wireless monitor and interface. Five cases are considered including LED, traffic light, stepping motor, DC volt meter, and temperature data logger on the IEEE 802.11 standard. The experiment results show the developed programs which can remote instruments on a monitor accurately.

Abstract: This research aims to purpose the new method, which is called Error Flag Framework (EFF) to enhance accuracy fingerprinting indoor positioning of wireless device by using machine learning algorithms. EFF is compared with well-known machine learning classifiers; i.e. Decision Tree, Naive Bayes, and Artificial Neural Networks, by exploiting the signal strength from limited information. The performance comparison is done in terms of accuracy of classification of positions, precision of distance classified, and effects of classification of positions on results from quantity of learning data. The result of this study can suggest that EFF can increase performance for indoor positioning of every well-known classifier, especially when the quantity of learning data is large enough. Hence, EFF is the alternate way for implementing in positioning software by using the fingerprinting method.

Abstract: We propose a resource allocation scheme based on Proportional Fairness (PF) for minimum bit rate guarantee in a multiuser, frequency-selective frame-based OFDMA system. Instead of considering subcarrier-and-bit allocation, we consider a more realistic scheduling which is performed at the beginning of each frame, while allowing time-slots multiplexing among active users. Our scheme aims to guarantee different minimum bit rates to different users, while throughput fairness among users is maintained. We formulate the optimization problem based on a multichannel proportional fairness objective function. Minimum bit rate guarantee is taken as the constraint. The optimization problem is solved by using the Lagrange multiplier method. Then, we use our fast cross-layer approach integrated to our optimization solution to schedule packets from finitely backlogged queues. Simulations with user mobility are conducted. The results show that the proposed scheme can serve users with satisfied minimum bit rate requirement. Furthermore, the simulation results also confirm throughput fairness among users.

Abstract: This paper proposes the several contention window adjustment schemes in backoff process as well-known backoff algorithm (BA) for improving the performance of wireless local area network (WLAN). In addition, this research introduces a new unsaturated discrete Markov chain model in fixed backoff stages and fixed contention window sizes technique (FBFC). The proposed contention window adjustment schemes are designed by applying the moment generating function concept in random variable and process theorem. Unsaturated throughput parameters are used to compare the performance of all contention window size adjustment techniques based on IEEE802.11b WLAN standards. The comparison results show that Bernoulli and Double adjustment schemes are good contention window size adjustments at light traffic load, and the Even contention window size adjustment operates well at high traffic load condition.