Design of Real-Time Large Field Video Display System Based on FPGA

Jiang Bo Chen; Yong Ming Qiao; Zhuo Wei Hou

doi:10.4028/www.scientific.net/AMR.945-949.1739

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 945-949Design of Real-Time Large Field Video Display...

Design of Real-Time Large Field Video Display System Based on FPGA

Abstract:

In order to realize the large field or view digital video images into PAL format analog video output,this article introduce a real-time display system of large visual field in the basis of FPGA. Apply the EP2S30F672I4 chip of the StraixII series to be the core processing unit, which is from the Altera; and the CSC12M25BMP19 camera, from the Teli, to be the image data source, with 25 Hz of output frame rate and a resolution of 2048 x 2048 on images. The Cameralink interface is adopted to be the data transmission channel between the camera and interface card, which carries out the configuration of the camera, image data acquisition, caching, image reduction and PAL format conversion, and finally accomplishes the image real-time display.This paper discusses the FPGA implementation of double bilinear interpolation algorithm, including image data frames buffer, the vertical and horizontal interpolation. The experiments results show that our expects are achieved by the algorithm and the hardware implementation.

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Periodical:

Advanced Materials Research (Volumes 945-949)

Pages:

1739-1743

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.945-949.1739

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Online since:

June 2014

Authors:

Jiang Bo Chen*, Yong Ming Qiao, Zhuo Wei Hou

Keywords:

Double Linear Interpolation, FPGA, Ping-Pong Operation, Real-Time Display

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* - Corresponding Author

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