Electrical Characterization of Interface Defects in MOS Structures Containing Silicon Nanoclusters

Abraham Arias; Nicola Nedev; Mario Curiel; Diana Nesheva; Emil Manolov; Benjamin Valdez; David Mateos; Oscar Contreras; Oscar Raymond; Jesus M. Siqueiros

doi:10.4028/www.scientific.net/AMR.976.129

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Effect of Substrate Temperature on the Properties of Hafnium Nitride Films Prepared by DC Sputtering
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Electrical Characterization of Interface Defects in MOS Structures Containing Silicon Nanoclusters
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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 976Electrical Characterization of Interface Defects...

Electrical Characterization of Interface Defects in MOS Structures Containing Silicon Nanoclusters

Abstract:

The effect of annealing temperature on the properties of c-Si wafer/SiO_x interface (x = 1.15 and 1.3) is studied by Transmission Electron Microscopy and Capacitance/Conductance-Voltage measurements. Furnace annealing for 60 min at 700 and 1000 °C is used to grow amorphous or crystalline Si nanoparticles. The high temperature process leads to an epitaxial overgrowth of the Si wafer and an increase of the interface roughness, 3-4 monolayers at 700 °C and 4-5 monolayers at 1000 °C. The increased surface roughness is in correlation with the higher density of electrically active interface states.

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Periodical:

Advanced Materials Research (Volume 976)

Pages:

129-132

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.976.129

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Online since:

June 2014

Authors:

Abraham Arias*, Nicola Nedev, Mario Curiel, Diana Nesheva, Emil Manolov, Benjamin Valdez, David Mateos, Oscar Contreras, Oscar Raymond, Jesus M. Siqueiros

Keywords:

Amorphous Nanoparticles, C-V, G-V, Interface Defects, MOS, Si Nanocrystals, TEM

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