Instruction Scheduling on a Pipelined Processor for Mechanical Measurements

Abstract:

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Pipeline processing provides us an effective way to enhance processing speed with low hardware costs. However, pipeline hazards are obstacles to the smooth pipelined execution of instructions. This paper analyzes the pipeline hazards occur in a pipeline processor designed for data processing in mechanical measurements. Instruction scheduling and register renaming are performed to eliminate hazards. The simulation experiments are performed, and the effectiveness is confirmed.

Info:

Periodical:

Key Engineering Materials (Volumes 381-382)

Edited by:

Wei Gao, Yasuhiro Takaya, Yongsheng Gao and Michael Krystek

Pages:

647-648

DOI:

10.4028/www.scientific.net/KEM.381-382.647

Citation:

H. Shen and N. Numata, "Instruction Scheduling on a Pipelined Processor for Mechanical Measurements", Key Engineering Materials, Vols. 381-382, pp. 647-648, 2008

Online since:

June 2008

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Price:

$35.00

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