Instruction Scheduling on a Pipelined Processor for Mechanical Measurements

Hong Shen; Nobuyoshi Numata

doi:10.4028/www.scientific.net/KEM.381-382.647

Paper Titles

Investigation on the Noise Separation in Watt Balance Experiments
p.619

Advanced Analog-to-Digital Conversion Using Voltage-to-Frequency Converters for Remote Sensors
p.623

Correlation Processing of the Signals of the Single-Fiber Intermode Interferometer with a Small Number of Excited Modes
p.627

Research on Automatic Flaw Classification and Feature Extraction of Ultrasonic Testing
p.631

Simulation of Profiles of Normal Ordinate Distribution
p.635

Processing Speed Acceleration of an Intelligent Communication Instrument
p.639

The Design and Use of F1 Softgauges for Validating Surface Metrology Software
p.643

Instruction Scheduling on a Pipelined Processor for Mechanical Measurements
p.647

The Influence of Form Deviations and Surface Topography of Micro-Components on the Uncertainty of their Geometrical Parameters
p.649

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Instruction Scheduling on a Pipelined Processor for Mechanical Measurements

Abstract:

Pipeline processing provides us an effective way to enhance processing speed with low hardware costs. However, pipeline hazards are obstacles to the smooth pipelined execution of instructions. This paper analyzes the pipeline hazards occur in a pipeline processor designed for data processing in mechanical measurements. Instruction scheduling and register renaming are performed to eliminate hazards. The simulation experiments are performed, and the effectiveness is confirmed.