Optimal Parameter Design of Solder Residue in Flip Chip Process by Using Taguchi Method

Abstract:

Because the solder residue was found in the manufacturing process which greatly affected the product quality, the purpose of this paper was to make the product quality improved and to find an optimal solution for process parameters in the flip chip process. The experimental testing was based on SMT manufacturing process. The amount and size of solder left on passive component in the process of manufacturing were considered as the quality traits. Since too many solders left on the passive component side during flux cleaning process, it was possible that the balling would be flowed into the chip, which caused the bump short in the chip and affected the quality of the product. In this paper, orthogonal array by using Taguchi method is adopted as the effective experimental method with the least experimental runs. Also, based on the quality evaluation of signal-to-noise ratio, the ANOVA is used to evaluate the effects of quality target according to the experimental results. The results reveal that the optimization in the process is confirmed. Therefore, this study can effectively improve the solder residue in semiconductor manufacturing process.

• Periodical: Key Engineering Materials (Volume 443)
• Pages: 543-548
• DOI: https://doi.org/10.4028/www.scientific.net/KEM.443.543
• Online since: June 2010
• Authors: Jian Long Kuo, Kai Lun Chao, Chun Cheng Kuo
• Keywords: Solder Bead, Solder Residue, Taguchi Method

References

[1] John H. Lau: Express packaging system, Low cost Flip Chip technologies for DCA, WLSP and PBGA assemblies, (2002).

[2] John H. Lau: Express packaging system. Inc, Solder joint reliability BGA, CSP, Flip Chip and fine pitch SMT assemblies, (2002).

[3] Ning-Cheng Lee: Reflow soldering process and troubleshooting: SMT, BGA, CSP and Flip Chip Technologies, (2001).

DOI: 10.1108/mi.2003.21820aae.003

[4] Leandro G. Barajas: Process Control in High-Noise Environments Using a Limited Number of Measurements，School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA, 30332, (2002).

DOI: 10.17775/cseejpes.2016.00043

[5] T. A. Nguty, N. N. Ekere, and A. Adebayo: Correlating Solder Paste Composition with Stencil Printing Performance，Electronics Manufacturing Engineering Research Group Department of Aeronautical, Mechanical and Manufacturing Engineering University of Salford, (1999).

DOI: 10.1109/iemt.1999.804837

[6] John H. Lau: Express packaging system, Low cost Flip Chip technologies for DCA, WLSP and PBGA assemblies, (2000).