The Design and Implementation of the Core Algorithm of Embedded Real-Time Image Compression Technology

Abstract:

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This paper presents a FPGA-based implementation of the core algorithm of embedded real-time image compression technology. The algorithm is based on JPEG image compression method which is the most widely used. For the key part of the image compression, made a kinds of fast algorithms of 2D-DCT calculation. The 2D-DCT is decomposed into two 1D-DCT computing, and within the FPGA multiplier and adder using a complex method, so that it greatly reduced the complexity of FPGA and improved the processing speed of the image. And it achieved real-time compression of image requirements.

Info:

Periodical:

Key Engineering Materials (Volumes 480-481)

Edited by:

Yanwen Wu

Pages:

1618-1622

DOI:

10.4028/www.scientific.net/KEM.480-481.1618

Citation:

T. Qu et al., "The Design and Implementation of the Core Algorithm of Embedded Real-Time Image Compression Technology", Key Engineering Materials, Vols. 480-481, pp. 1618-1622, 2011

Online since:

June 2011

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Price:

$35.00

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