The Design and Implementation of the Core Algorithm of Embedded Real-Time Image Compression Technology

Abstract:

This paper presents a FPGA-based implementation of the core algorithm of embedded real-time image compression technology. The algorithm is based on JPEG image compression method which is the most widely used. For the key part of the image compression, made a kinds of fast algorithms of 2D-DCT calculation. The 2D-DCT is decomposed into two 1D-DCT computing, and within the FPGA multiplier and adder using a complex method, so that it greatly reduced the complexity of FPGA and improved the processing speed of the image. And it achieved real-time compression of image requirements.

• Periodical: Key Engineering Materials (Volumes 480-481)
• Pages: 1618-1622
• DOI: https://doi.org/10.4028/www.scientific.net/KEM.480-481.1618
• Online since: June 2011
• Authors: Tao Qu, Cong Tang, Yu Yu Zhang
• Keywords: Embedded, JPEG 2D-DCT, Real-Time

References

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