A Dicode Signaling Scheme for Capacitively Coupled Interface

Yasushi Yuminaka; Kyohei Kawano

doi:10.4028/www.scientific.net/KEM.497.296

Paper Titles

The Parameterization of All Disturbance Observers for Discrete-Time Plants with Input Disturbance
p.197

A Design Method for Internal Model Controllers for Multiple-Input/Multiple-Output Unstable Plant
p.210

A Design Method for Two-Degree-of-Freedom Modified Smith Predictors for Multiple-Input/Multiple-Output Time-Delay Plants
p.221

Study on the Model Feedback Control System for a Class of Non-Minimum Phase Systems
p.234

The Parameterization of All Plants Stabilized by Proportional Controller Formultiple-Input/Multiple-Output Plant
p.246

A Design Method for Two-Degree-of-Freedom Multi-Period Repetitive Control Systems with the Specified Frequency Characteristic
p.255

Architecture of High-Efficiency Digitally-Controlled Class-E Power Amplifier
p.273

Single Inductor DC-DC Converter with Independent Bipolar Outputs Using Charge Pump
p.285

A Dicode Signaling Scheme for Capacitively Coupled Interface
p.296

HomeKey Engineering MaterialsKey Engineering Materials Vol. 497A Dicode Signaling Scheme for Capacitively Coupled...

A Dicode Signaling Scheme for Capacitively Coupled Interface

Abstract:

In this paper, we present a bandwidth-efficient partial-response signaling scheme for capacitivelycoupled chip-to-chip data transmission to increase data rate. Partial-response coding is knownas a technique that allows high-speed transmission while using a limited frequency bandwidth, by allowingcontrolled intersymbol interference (ISI). Analysis and circuit simulation results are presentedto show the impact of duobinary (1+D) and dicode (1-D) partial-response signaling for capacitivelycoupled interface.