A 2nd-Order PWM Pre-Emphasis Technique and its Experimental FPGA Implementation

Yasushi Yuminaka; Shingo Ishida; Kenichi Henmi

doi:10.4028/www.scientific.net/KEM.534.227

Paper Titles

A Study on the Class of Model Feedback Controllers Formultiple-Input/Multiple-Output Non-Minimum Phase System
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An Analytical Study on Jitter Accumulation in Interleaved Phase Frequency Detectors for High-Accuracy On-Chip Jitter Measurements
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A High Efficiency, Extended Load Range Boost Regulator Optimized Forenergy Harvesting Applications
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Single Inductor Bipolar Outputs DC-DC Converter with Current Mode Control Circuit
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A 2nd-Order PWM Pre-Emphasis Technique and its Experimental FPGA Implementation
p.227

Multiple-Valued Pulse-Position Modulation Techniques for Efficient Data Transmission
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Desialylation of N-Linked Carbohydrate Chain of Fibrinogen
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Verification of Photochemically Induced Crystallization Mechanism of Proteins by Dimer Addition
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Fabrication of Hole-Type Microcantilevers Using FIB and its Evaluations
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HomeKey Engineering MaterialsKey Engineering Materials Vol. 534A 2nd-Order PWM Pre-Emphasis Technique and its...

A 2nd-Order PWM Pre-Emphasis Technique and its Experimental FPGA Implementation

Abstract:

In this paper, a Pulse-Width Modulation (PWM) pre-emphasis technique is extended to a2nd-order version to equalize a higher-order transfer function of an interconnection inside/betweenVLSI chips. The PWM pre-emphasis method does not change the pulse amplitude as for conventionalFIR pre-emphasis, but instead exploits timing resolution. As a proof of concept, a 2nd-order timedomainpre-emphasis technique is designed and implemented using an FPGA to demonstrate thecapability of compensating for deterioration of signals caused by interconnections with higher-ordertransfer functions.