A Fourth-Order MASH Sigma-Delta Modulator in Inertial Sensors

Abstract:

The theory of a Sigma-Delta modulator is introduced in this paper. Based on this theory, a feedback 2-1-1 multi-stage-noise-shaping (MASH) sigma-delta modulator is designed, and the coefficients of the modulator are calculated. The system-level simulation results show that the effective number of bits (ENOB) is 24 bits when the signal bandwidth is 1 kHz and the over-sampling (OSR) rate is 128. Then the circuits of modulator are designed, including integrator, comparator, multi-phase clock and the noise cancelling logic. The whole modulator is simulated in Cadence, the signal to noise ratio (SNR) of the modulator is 125.4dB, and the ENOB is 21.1bits, which meet the technical requirements of the sensor.

• Periodical: Key Engineering Materials (Volumes 562-565)
• Pages: 311-316
• DOI: https://doi.org/10.4028/www.scientific.net/KEM.562-565.311
• Online since: July 2013
• Authors: Xiao Wei Liu, Qiang Li, Guan Nan Sun, Wen Yan Liu
• Keywords: Analog-Digital Hybrid, Inertial Sensors, Mash, Sigma-Delta Modulator, SNR

References

[1] I.Fujimori, L.Longo, A.Hairapetian, K.Seiyama, S.Kosic and J.Cao, "A 90-dB SNR 2.5-MHzoutput-rate ADC using cascaded multibit deltasigmamodulation at 8x oversampling ratio," IEEE J. Solid-State Circuits, 2000, pp.1820-1828.

DOI: 10.1109/isscc.2000.839806

[2] K.Vleugels, S.Rabii and B.Wooley, "A 2.5-V sigma-delta modulator for broadband communications applications," IEEE J. Solid-State Circuits, 2001, pp.1887-1899.

DOI: 10.1109/4.972139

[3] J.Silva, U.Moon, and G.Temes, "Low-distortion delta-sigma topologies for MASH architectures," Proceedings - IEEE International Symposium on Circuit and Systems, 2004, pp. I1144-I1147.

DOI: 10.1109/iscas.2004.1328402

[4] Z.Sohrabi and M.Yavari, "A 13 bit 10MHz bandwidth MASH 3-2 ΣΔ modulator in 90 nm CMOS," International Journal of Circuit Theory and Applications, 2012.

DOI: 10.1002/cta.1816

[5] K.Peter, A.Wiesbauer, T.Sun, U.Moon, J.Stonick and G.Temes, "Adaptive digital correction of analog errors in MASH ADC," IEEE Transations on Circuit and System, 2000, pp.629-638.

DOI: 10.1109/82.850422

[6] A.Oquz, K.Jinseok, A.Philip, "A 1.5V multirate multibit sigma-delta modulator for GSM/WCDMA in a 90nm digital CMOS process," Proceedings – IEEE International Symposium on Circuit and Systems, 2005, pp.5577-5580.

DOI: 10.1109/iscas.2005.1465901

[7] Y.Geerts S.J. Steyaert and W.Sansen, "A Hign-performance Multibit Sigma-Delta CMOS ADC," IEEE Journal of Solid-State Circuit, 2000, pp.1432-1444.

DOI: 10.1109/4.890296