A Hierarchical Self-Organizing Neural Network for Automatic Wafer Defect Inspection

Article Preview

Abstract:

The wafer defect inspection is an important process before die packaging. The defective regions were usually identified through visual judgment with the aid of a scanning electron microscope. Dozens of people visually check dies and mark their regions manually. Thus, potential misjudgment may be introduced due to human fatigue. In addition, the process can incur significant personnel costs. Self-Organizing Neural Networks (SONNs) have been proven to have the capabilities of unsupervised auto-clustering. In this paper, a hierarchical self-organizing neural networks (HSONN) with consideration of multiple textural information is proposed to replace the traditional electrical testing and the human inspection processes. The proposed HSONN is consists of 3 layers, each layer is a specific cluster to separate the block of wafer image into normal and defective regions. The suspicious defective regions are used as inputs to the next layer of HSONN for subsequent classification of the defective regions. Through the hierarchical classify, the output of the 3th layer denotes the detecting defective regions. Based on real-world data, the experimental results show that the proposed method successfully identifies the defective regions on wafers with good performances.

You might also be interested in these eBooks

Info:

Periodical:

Materials Science Forum (Volumes 505-507)

Pages:

1147-1152

Citation:

Online since:

January 2006

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2006 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

[1] J. -M. Zang, R. -M. Lin, and M. -J. J. Wang, The development of an automatic post-sawing inspection system using computer vision techniques, Computers in Industry, vol. 40, pp.51-60, (1999).

DOI: 10.1016/s0166-3615(99)00009-3

Google Scholar

[2] Chao-Ton Su, Taho Yang, Chir-Mour Ke, Neural-network approach for semiconductor wafer post-sawing inspection, IEEE Transactions on Semiconductor Manufacturing , vol. 15 , No. 2, pp.260-266, (2002).

DOI: 10.1109/66.999602

Google Scholar

[3] Chenn-Jung Huang, Chi-Feng Wu, Chua-Chin Wan, Image processing techniques for wafer defect cluster identification, IEEE Design & Test of Computers, vol. 19, no. 2, pp.44-48, (2002).

DOI: 10.1109/54.990441

Google Scholar

[4] Kenneth W. Tobin, Jr., Thomas P. Karnowski, Fred Lakhani, Integrated applications of inspection data in the semiconductor manufacturing environment, SPIE, Metrology-based Control for Micro-Manufacturing; vol. 4275, pp.31-40, (2001).

DOI: 10.1117/12.429361

Google Scholar

[5] Mital, D.P. Teoh, E. K, Computer based wafer inspection system, " Proceedings. IECON , 91., 1991 Proceeding of International Conference on Industrial Electronics, Control and Instrumentation, vol. 3, pp.2497-2503, (1991).

DOI: 10.1109/iecon.1991.238937

Google Scholar

[6] Chuan-Yu Chang, Jia-Wei Chang, Mu Der Jeng, An Unsupervised Self-Organizing Neural Network for Automatic Semiconductor Wafer Defect Inspection, in Proceeding of IEEE International Conference on Robotics and Automation, pp.18-22, (2005).

DOI: 10.1109/robot.2005.1570570

Google Scholar

[7] Simon Haykin, Neural Networks. A Comprehensive Foundation, Prentice-Hall International, Inc. (1999).

Google Scholar

[8] M. Cheriet, J. N. Said, and C. Y. Suen, A recursive thresholding technique for image segmentation, IEEE Trans. On Image processing, vol. 7, pp.918-921, (1998).

DOI: 10.1109/83.679444

Google Scholar