Contactless Chip Module Defect Reduction

Thunwarat Sawatsuphaphon; Parames Chutima

doi:10.4028/www.scientific.net/SSP.305.59

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HomeSolid State PhenomenaSolid State Phenomena Vol. 305Contactless Chip Module Defect Reduction

Contactless Chip Module Defect Reduction

Abstract:

This research was conducted in a manufacturing company that produces integrated circuits for global customers. The purpose of this research was to reduce defect rate from the assembly department that affected to product lots on hold at the test department for the contactless chip module package which had an increasing product lots on hold rate of 9.5% in March 2019 based on the reject criteria V_limiter (REQA). The potential cause of defect came from die crack. In order to reduce defect rate, the 5 steps of DMAIC Six Sigma methodology were applied in this research to identify the root cause of the problem and establish effective actions. After the improvement, the product (lots) on hold criteria V_limiter (REQA) was reduced from 9.5% to 5.82% in July 2019.

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Periodical:

Solid State Phenomena (Volume 305)

Pages:

59-64

DOI:

https://doi.org/10.4028/www.scientific.net/SSP.305.59

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Online since:

June 2020

Authors:

Thunwarat Sawatsuphaphon, Parames Chutima*

Keywords:

Contactless Chip Module, Fault Tree Analysis, Process Improvement, Six Sigma

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References

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