Modelling Geometry of Technological Masks in Lateral Etching Processes


Article Preview

A model of the evolution geometry technological masks and underlaying layers in the lateral etching processes is created for analysis and design of new self-alignment and self-formation technologies semiconductor devices and integrated circuits. The results of the simulation for the different configurations masks and selectivities of the underlaying layers have been presented.



Solid State Phenomena (Volumes 97-98)

Edited by:

Stepas Janušonis




R. Navickas and R. Ciulada, "Modelling Geometry of Technological Masks in Lateral Etching Processes", Solid State Phenomena, Vols. 97-98, pp. 235-238, 2004

Online since:

April 2004




[1] S. Janusonis, and V. Janusoniene: Self-Formation in Semiconductor Technology (Mokslas, Vilnius, 1985), p.192 (in Russian).

[2] R. Navickas: Rewiew of Electronics – Vol. 3 Microelectronics (Moscow, CSII “Electronics”) No. 1(1181) (1986), p.43 (in Russian).

[3] R. Navickas: Electronics and Electrical Engineering (Kaunas, Technologija) No. 3(26) (2000), pp.72-77 (in Lithuanian).

[4] R. Navickas: Electronics and Communications (Kiev) No. 18 (2003), pp.149-154 (in Russian).

[5] J. -W. Park, S. Mohammadi, D. Pavlidis et al.: Solid-State Electronics Vol. 44 (2000), p.2059- (2067).

[6] Q. Lee, S. Martin, D. Mensa et al.: IEEE Electron Device Letters Vol. 20, No. 8 (1999), pp.396-398.

[7] R. Navickas, R. Ciulada: Information Technology and Control (Kaunas, Technologija) No. 4(25) (2002), pp.65-68.