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Drift-Free, 50 A, 10 kV 4H-SiC PiN Diodes with Improved Device Yields

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Abstract:

The path to commericializing a 4H-SiC power PiN diode has faced many difficult challenges. In this work, we report a 50 A, 10 kV 4H-SiC PiN diode technology where good crystalline quality and high carrier lifetime of the material has enabled a high yielding process with VF as low as 3.9 V @ 100 A/cm2. Furthermore, incorporation of two independent basal plane dislocation reduction processes (LBPD 1 and LBPD 2) have produced a large number of devices that exhibit a high degree of forward voltage stability with encouraging reverse blocking capability. This results in a total yield (forward, 10 kV blocking, and drift) of >20% for 8.7 mm x 8.7 mm power PiN diode chips—the largest SiC chip reported to date.

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Periodical:

Materials Science Forum (Volumes 483-485)

Pages:

965-968

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.483-485.965

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Online since:

May 2005

Authors:

Mrinal K. Das, Joseph J. Sumakeris, Brett A. Hull, Jim Richmond, Sumi Krishnaswami, Adrian R. Powell

Keywords:

Basal Plane Dislocation (BPD), Device Yield, High Voltage (HV), PiN Diode, Vf Drift

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© 2005 Trans Tech Publications Ltd. All Rights Reserved

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References

[1] M.K. Das: Latest Advances in 4H-SiC PiN and MOS Power Devices (International Semiconductor Device Research Symposium, Washington, DC, December 2003).

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DOI: 10.1007/s11664-005-0107-4

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