Authors: Jean Lorenzzi, Romain Esteve, Nikoletta Jegenyes, Sergey A. Reshanov, Adolf Schöner, Gabriel Ferro
Abstract: In this work we report on the growth and preparation of 3C-SiC(111) material for metal-oxide-semiconductor (MOS) application. In order to achieve reasonable material quality to prepare MOS capacitors several and crucial steps are needed: 1) heteroepitaxial growth of high quality 3C-SiC(111) layer by vapour-liquid-solid mechanism on 6H-SiC(0001) substrate, 2) surface polishing, 3) homoepitaxial re-growth by chemical vapour deposition and 4) use of an advanced oxidation process combining plasma enhanced chemical vapour deposition (PECVD) SiO2 and short post-oxidation steps in wet oxygen. Combining all these processes the interface traps density (Dit)can be drastically decreased down to 1.2 1010 eV-1cm-2 at 0.63 eV below the conduction band. To our knowledge, these values are the best ever reported for SiC material in general and 3C-SiC in particular.
433
Authors: Thanos Tsirimpis, S. Beljakova, Bernd Zippelius, Heiko B. Weber, Gerhard Pensl, M. Krieger, Hiroyuki Nagasawa, Takamitsu Kawahara, Naoki Hatta, Kuniaki Yagi, Hidetsugu Uchida, Motoki Kobayashi, Adolf Schöner
Abstract: p-type 3C-SiC samples were implanted by iron (Fe) and investigated by means of deep level transient spectroscopy (DLTS). Corresponding argon (Ar) profiles with similar implantation damage were implanted in order to distinguish between iron-related defects and defects caused by implantation damage. Two donor-like iron-related centers were identified in p-type 3C-SiC.
265
Authors: Mietek Bakowski, Adolf Schöner, Ingemar Petermann, Susan Savage
Abstract: This paper describes a novel design to achieve sensitive and stable performance of an avalanche photodiode based on silicon carbide material. The design includes a field-stopping layer with limited extension, and junction termination, in order to achieve avalanche multiplication only in the central region of the device. Also, sensitivity is increased by the achievement of a rectangular field distribution, and full depletion of the absorption region by the onset of avalanche multiplication. Evaluation of devices produced with this design show that a low leakage current and a sharp and stable avalanche breakdown point around 120V is achieved. Optical responsivity to radiation of wavelength 200 to 400 nm is shown to increase with increasing applied reverse bias, until a factor of 8 increase is achieved at the breakdown voltage.
1089
Authors: Romain Esteve, Adolf Schöner, Sergey A. Reshanov, Carl Mikael Zetterling
Abstract: The electrical properties of oxides fabricated on n-type 3C-SiC (001) using wet oxidation and an advanced oxidation process combining SiO2 deposition with rapid post oxidation steps have been compared. Two alternative SiO2 deposition techniques have been studied: the plasma enhanced chemical vapor deposition (PECVD) and the low pressure chemical vapor deposition (LPCVD). The post-oxidized PECVD oxide is been demonstrated to be beneficial in terms of interface traps density and reliability.
829
Authors: Reza Ghandi, Martin Domeij, Romain Esteve, Benedetto Buono, Adolf Schöner, Ji Sheng Han, Sima Dimitrijev, Sergey A. Reshanov, Carl Mikael Zetterling, Mikael Östling
Abstract: In this work, the electrical performance in terms of maximum current gain, ON-resistance and blocking capability has been compared for 4H-SiC BJTs passivated with different surface passivation layers. Variation in BJT performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for PECVD deposited SiO2 which was annealed in N2O ambient at 1100 °C during 3 hours. Variations in breakdown voltage for different surface passivations were also found, and this is attributed to differences in fixed oxide charge that can affect the optimum dose of the high voltage JTE termination.
661
Authors: Michael Weidner, Lia Trapaidze, Gerhard Pensl, Sergey A. Reshanov, Adolf Schöner, Hisayoshi Itoh, Takeshi Ohshima, Tsunenobu Kimoto
Abstract: Intrinsic defects in 3C-SiC are generated by implantation of H+- and He+-ions or irra¬diation with high energy electrons. The defect parameters and the thermal stability of the observed defects are determined. The capture-cross-section of the W6-center is directly measured by variation of the filling pulse length. The charge state of the W6-center is obtained from double-correlated DLTS investigations according to the Poole-Frenkel effect.
439
Authors: Svetlana Beljakowa, M. Krieger, Thomas Frank, Gerhard Pensl, Lia Trapaidze, Naoki Hatta, Masayuki Abe, Hiroyuki Nagasawa, Adolf Schöner
Abstract: 3C-SiC/SiO2-capacitors are fabricated by over-oxidation of an implanted Gaussian
nitrogen (N) profile and investigated by conductance spectroscopy. A double peak structure is
observed in the conductance spectra indicating two types of traps, which change their charge state at
identical time constant, however, which are located at different energy positions in the bandgap of
3C-SiC. The experimental G/w-V and C-V characteristics are simulated and the existence of two
types of traps is verified in the framework of a theoretical model.
727
Authors: Margareta K. Linnarsson, J. Isberg, Adolf Schöner, Anders Hallén
Abstract: The boron diffusion in three kinds of group IV semiconductors: silicon, silicon carbide
and synthetic diamond has been studied by secondary ion mass spectrometry. Ion implantation of
300 keV, 11B-ions to a dose of 21014 cm-2 has been performed. The samples are subsequently
annealed at temperatures ranging from 800 to 1650 °C for 5 minutes up to 8 hours. In silicon and
silicon carbide, the boron diffusion is attributed to a transient process and the level of out-diffusion
is correlated to intrinsic carrier concentration. No transient, out-diffused, boron tail is revealed in
diamond at these temperatures.
453
Authors: Adolf Schöner, Naohiro Sugiyama, Yuuichi Takeuchi, Rajesh Kumar Malhan
Abstract: The in-situ doping of aluminum and nitrogen in migration enhanced embedded epitaxy (ME3) is investigated with the aim to apply it to the realization and fabrication of all-epitaxial, normally-off 4H-SiC JFET devices. This ME3 process consists of the epitaxial growth of an n-doped channel and a highly p-doped top gate in narrow trenches. We found that the nitrogen doping in the n-channel (a-face) is a factor 1.5 higher than layers grown with the same process on Si-face wafers. Due to the low C/Si ratio and the low silane flow rate used in the ME3 process, the growth of the p-doped top gate needs high flow rates of the aluminum precursor trimethylaluminum for several hours, which contaminates the CVD reactor and causes aluminum memory effects. These aluminum memory effects can be reduced by an extra high temperature bake-out run.
175
Authors: Naohiro Sugiyama, Yuuichi Takeuchi, Mitsuhiro Kataoka, Adolf Schöner, Rajesh Kumar Malhan
Abstract: The migration enhanced embedded epitaxy (ME3) mechanism and 2D dopant distribution of the embedded trench region is investigated with the aim to realize the all-epitaxial, normally-off junction field effect transistor (JFET). We found that the embedded growth consists of two main components. First one is the direct supply without gas scattering and the other one is the surface migration supply via the trench opening edge, which dominate the ME3 process. An inhomogeneous 2D distribution of Aluminum (Al) concentration was revealed for the first time in the 4H-SiC embedded trench regions by the combined analysis of secondary ion mass spectrometry (SIMS) and scanning spreading resistance microscopy (SSRM) results. The maximum variation of Al concentration in the trench is estimated to be about 4-times, which suggests that the Al concentration is highest for the (0001) plane and lowest for the trench corner (1-10x) plane. Al concentration in the (1-100) plane, which determines the JFET p-gate doping level is 1.5-times lower than (0001) plane for trench region fabricated on Si-face wafers.
171