Authors: Adrian R. Powell, Joseph J. Sumakeris, Yuri Khlebnikov, Michael J. Paisley, R.T. Leonard, Eugene Deyneka, Sumit Gangwal, Jyothi Ambati, V. Tsevtkov, Jeff Seaman, Andy McClure, Chris Horton, Olek Kramarenko, Varad Sakhalkar, M. O’Loughlin, Albert A. Burk, J.Q. Guo, Michael Dudley, Elif Balkas
Abstract: The growth of large diameter silicon carbide (SiC) crystals produced by the physical vapor transport (PVT) method is outlined. Methods to increase the crystal diameters, and to turn these large diameter crystals into substrates that are ready for the epitaxial growth of SiC or other non homogeneous epitaxial layers are discussed. We review the present status of 150 mm and 200 mm substrate quality at Cree, Inc. in terms of crystallinity, dislocation density as well as the final substrate surface quality.
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Authors: Joseph J. Sumakeris, R.T. Leonard, Eugene Deyneka, Yuri Khlebnikov, Adrian R. Powell, Jeff Seaman, Michael J. Paisley, V. Tsevtkov, Jian Qiu Guo, Yu Yang, Michael Dudley, Elif Balkas
Abstract: Definitive correlations are presented between specific types of dislocations identified via Synchrotron White Beam X-Ray Topography (SWBXRT) and identified via selective etching of 4H-SiC substrates. A variety of etch conditions and the results on different faces of SiC substrates and epiwafers are examined. Hillocks formed on the carbon face of the substrate after KOH etching correlate very well to TSDs identified via SWBXRT. Topography of substrates and of vertical crystal slices reveals a large proportion of Threading Mixed character Dislocations (TMDs) in the population of Threading Screw Dislocations.
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Authors: Elif Berkman, R.T. Leonard, Michael J. Paisley, Y. Khlebnikov, Michael J. O'Loughlin, Albert A. Burk, Adrian R. Powell, D.P. Malta, E. Deyneka, M.F. Brady, I. Khlebnikov, Valeri F. Tsvetkov, H.McD. Hobgood, Joseph J. Sumakeris, C. Basceri, Vijay Balakrishna, Calvin H. Carter Jr., C. Balkas
Abstract: Availability of high-quality, large diameter SiC wafers in quantity has bolstered the commercial application of and interest in both SiC- and nitride-based device technologies. Successful development of SiC devices requires low defect densities, which have been achieved only through significant advances in substrate and epitaxial layer quality. Cree has established viable materials technologies to attain these qualities on production wafers and further developments are imminent. Zero micropipe (ZMP) 100 mm 4HN-SiC substrates are commercially available and 1c dislocations densities were reduced to values as low as 175 cm-2. On these low defect substrates we have achieved repeatable production of thick epitaxial layers with defect densities of less than 1 cm-2 and as low as 0.2 cm-2. These accomplishments rely on precise monitoring of both material and manufacturing induced defects. Selective etch techniques and an optical surface analyzer is used to inspect these defects on our wafers. Results were verified by optical microscopy and x-ray topography.
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Authors: Brett A. Hull, Joseph J. Sumakeris, Michael J. O'Loughlin, Q. Jon Zhang, Jim Richmond, Adrian R. Powell, Michael J. Paisley, Valeri F. Tsvetkov, A. Hefner, Angel Rivera
Abstract: DC characteristics and reverse recovery performance of 4H-SiC Junction Barrier Schottky (JBS)
diodes capable of blocking in excess of 10 kV with forward conduction of 20 A at a forward voltage
of less than 4 V are described. Performance comparisons are made to a similarly rated 10 kV
4H-SiC PiN diode. The JBS diodes show a significant improvement in reverse recovery stored
charge as compared to PiN diodes, showing half of the stored charge at 25°C and a quarter of the
stored charge at 125°C when switched to 3 kV blocking. These large area JBS diodes were also
employed to demonstrate the tremendous advances that have recently been made in 4H-SiC
substrate quality.
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Authors: Anant K. Agarwal, Albert A. Burk, Robert Callanan, Craig Capell, Mrinal K. Das, Sarah K. Haney, Brett A. Hull, Charlotte Jonas, Michael J. O'Loughlin, Michael O`Neil, John W. Palmour, Adrian R. Powell, Jim Richmond, Sei Hyung Ryu, Robert E. Stahlbush, Joseph J. Sumakeris, Q. Jon Zhang
Abstract: In this paper, we review the state of the art of SiC switches and the technical issues which
remain. Specifically, we will review the progress and remaining challenges associated with SiC
power MOSFETs and BJTs. The most difficult issue when fabricating MOSFETs has been an
excessive variation in threshold voltage from batch to batch. This difficulty arises due to the fact that
the threshold voltage is determined by the difference between two large numbers, namely, a large
fixed oxide charge and a large negative charge in the interface traps. There may also be some
significant charge captured in the bulk traps in SiC and SiO2. The effect of recombination-induced
stacking faults (SFs) on majority carrier mobility has been confirmed with 10 kV Merged PN
Schottky (MPS) diodes and MOSFETs. The same SFs have been found to be responsible for
degradation of BJTs.
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Authors: R.T. Leonard, Y. Khlebnikov, Adrian R. Powell, C. Basceri, M.F. Brady, I. Khlebnikov, Jason R. Jenny, D.P. Malta, Michael J. Paisley, Valeri F. Tsvetkov, R. Zilli, E. Deyneka, H.McD. Hobgood, Vijay Balakrishna, Calvin H. Carter Jr.
Abstract: Recent advances in PVT c-axis growth process have shown a path for eliminating micropipes in 4HN-SiC, leading to the demonstration of zero micropipe density 100 mm 4HN-SiC wafers. Combined techniques of KOH etching and cross-polarizer inspections were used to confirm the absence of micropipes. Crystal growth studies for 3-inch material with similar processes have demonstrated a 1c screw dislocation median density of 175 cm-2, compared to typical densities of 2x103 to 4x103 cm-2 in current production wafers. These values were obtained through optical scanning analyzer methods and verified by x-ray topography.
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Authors: Albert A. Burk, Michael J. O'Loughlin, Joseph J. Sumakeris, C. Hallin, Elif Berkman, Vijay Balakrishna, Jonathan Young, Lara Garrett, Kenneth G. Irvine, Adrian R. Powell, Y. Khlebnikov, R.T. Leonard, C. Basceri, Brett A. Hull, Anant K. Agarwal
Abstract: The development of SiC bulk and epitaxial materials is reviewed with an emphasis on epitaxial growth using high-throughput, multi-wafer, vapor phase epitaxial (VPE) warm-wall planetary reactors. It will be shown how the recent emergence of low-cost high-quality 100-mm diameter epitaxial SiC wafers is enabling the economical production of advanced wide-bandgap Power–Switching devices.
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Authors: K.W. Kirchner, Kenneth A. Jones, Michael A. Derenge, Michael Dudley, Adrian R. Powell
Abstract: Double and triple crystal rocking curve and peak position maps are constructed for a 4HSiC
wafer for the symmetric (0 0 0 8) reflection in the normal position, the same reflection for a
sample rotated 90º, and an asymmetric (1 23 6) reflection for the wafer in the normal position.
These measurements were corrected for the ‘wobble’ in the instrument by scanning a 4” (1 1 1) Si
wafer and assuming that the Si wafer was perfect and attributing the variations in the measurements
to instrumental error. The x-ray measurements are correlated with a cross polar image, etch pit
density map, white beam transmission x-ray topograph, and a laser light scan.
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Authors: Albert A. Burk, Michael J. O'Loughlin, Michael J. Paisley, Adrian R. Powell, M.F. Brady, R.T. Leonard, D.A. McClure
Abstract: Experimental results are presented for SiC epitaxial layer growth employing a large-area,
up to 8x100-mm, warm-wall planetary SiC-VPE reactor. This high-throughput reactor has been
optimized for the growth of uniform 0.01 to 80-micron thick, specular, device-quality SiC epitaxial
layers with low background doping concentrations of <1x1014 cm-3 and intentional p- and n-type
doping from ~1x1015 cm-3 to >1x1019 cm-3. Intrawafer layer thickness and n-type doping uniformity
(σ/mean) of ~2% and ~8% have been achieved to date in the 8x100-mm configuration. The total
range of the average intrawafer thickness and doping within a run are approximately ±1% and ±6%
respectively.
159
Authors: Mrinal K. Das, Joseph J. Sumakeris, Brett A. Hull, Jim Richmond, Sumi Krishnaswami, Adrian R. Powell
Abstract: The path to commericializing a 4H-SiC power PiN diode has faced many difficult
challenges. In this work, we report a 50 A, 10 kV 4H-SiC PiN diode technology where good crystalline quality and high carrier lifetime of the material has enabled a high yielding process with VF as low as 3.9 V @ 100 A/cm2. Furthermore, incorporation of two independent basal plane dislocation reduction processes (LBPD 1 and LBPD 2) have produced a large number of devices
that exhibit a high degree of forward voltage stability with encouraging reverse blocking capability. This results in a total yield (forward, 10 kV blocking, and drift) of >20% for 8.7 mm x 8.7 mm power PiN diode chips—the largest SiC chip reported to date.
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