Papers by Author: Hiroyuki Nagasawa

Abstract: The correlation between leakage current and stacking fault (SF) density in p-n diodes fabricated on 3C-SiC homo-epitaxial layer is investigated. The leakage current density at reverse bias strongly depends on the SF density; an increase of one order of magnitude in the SF density enhances the leakage current by five orders of magnitude at a reverse bias of 400 V. In order to obtain commercially suitable MOSFETs with 10-4Acm-2 at 600V, the SF density has to be reduced below 6×104 cm-2. Photoemission caused by hot electrons, which travel along a leakage path, can be observed at the crossing between a SF and the edge of p-well region; where the maximum electric field is induced. The mechanism of the leakage current is discussed in detail in a separate paper.

Abstract: 3C-SiC/SiO2-capacitors are fabricated by over-oxidation of an implanted Gaussian nitrogen (N) profile and investigated by conductance spectroscopy. A double peak structure is observed in the conductance spectra indicating two types of traps, which change their charge state at identical time constant, however, which are located at different energy positions in the bandgap of 3C-SiC. The experimental G/w-V and C-V characteristics are simulated and the existence of two types of traps is verified in the framework of a theoretical model.

Abstract: In 3C-SiC MOSFETs, planar defects like anti-phase boundaries (APBs) and stacking-faults (SFs) reduce the breakdown voltage and induce leakage current. Although the planar defect density can be reduced by growing 3C-SiC on undulant-Si substrate, specific type of SFs, which expose the Si-face, remains on the (001) surface. Those SFs increase the leakage current in devices made with 3C-SiC. In order to eliminate the residual SFs, an advanced SF reduction method involving polarity conversion and homo-epitaxial growth was developed. This method is called switch-back epitaxy (SBE) and consists of the conversion of the SF surface polarity from Si-face to C-face and following homo-epitaxial growth. The reduction of the SF density in SBE 3C-SiC results in a tremendous improvement of the device performance. The combination of the achieved blocking voltage with the demonstrated high current capability indicates the potential of 3C-SiC vertical MOSFETs for high and medium power electronic applications such as electric and hybrid electric vehicle (EV/HEV) motor drives.

Abstract: Selenium (Se) and tellurium (Te) ions are implanted into n-type 6H-, 4H- and 3C-SiC epilayers. Double-correlated deep level transient spectroscopy investigations reveal that both Se and Te atoms form double donors in SiC. The number of double donors observed corresponds to the number of inequivalent lattice sites of the particular SiC polytype. This observation is a strong hint that Se and Te atoms reside on lattice sites. The activation energies FEa of Te double donors are larger than the corresponding ones of Se double donors.

Abstract: Vertical DMOSFET devices with varying size from single cell to 3x3 mm2 large devices have been realized. The investigated devices had hexagonal and square unit cell designs with 2 $m and 4 $m channel length. The p-body was aluminum implanted and the source was nitrogen or phosphorus implanted. Low temperature Ti/W contacts were evaluated.

Abstract: Cubic GaN, AlxGa1-xN/GaN and InyGa1-yN/GaN multiple quantum well (MQW) layers were grown by plasma assisted molecular beam epitaxy on 200 &m thick free standing 3C-SiC substrates. The influence of the surface roughness of the 3C-SiC substrates and the influence of metal coverage during growth are discussed. Optimum growth conditions of c-III nitrides exist, when a one monolayer Ga coverage is formed at the growing surface. The improvement of the structural properties of cubic III-nitride layers and multilayers grown on 3C-SiC substrates is demonstrated by 1 μm thick c-GaN layers with a minimum x-ray rocking curve width of 16 arcmin, and by c-AlGaN/GaN and c-InGaN/GaN MQWs which showed up to five satellite peaks in X-ray diffraction, respectively.

Abstract: A new technique that reduces stacking fault (SF) density in 3C-SiC, termed switch-back epitaxy (SBE), is demonstrated regarding its effects on morphological and electrical properties. SBE is a homoepitaxial growth process on backside of 3C-SiC grown on undulant-Si. The key feature of SBE, the surface polarity of residual SFs in 3C-SiC, which cannot be erased by heteroepitaxial growth on undulant-Si, is converted from the Si-face to the C-face. The SF density on the surface of 3C-SiC grown by SBE shows a remarkable decrease to one-seventh lower than that on undulant- Si. The leakage current of pn-diode epitaxially fabricated on the 3C-SiC substrate grown by SBE decreases to as low as one-thirtieth that on 3C-SiC substrate grown without SBE. These results suggest that SBE eliminates the SFs on the surface of 3C-SiC and subsequently reduces the leakage current at pn-junction thus fabricated.

Abstract: Visible and deep UV Raman measurements have been applied to investigate the structural and electrical properties of stacking disordered 3C-SiC crystals. It is found that free-carrier density shows the significant dependence on the density of stacking faults in 3C-SiC. The density of stacking faults has been estimated from the comparison between experimentally obtained Raman spectra and Raman intensity profiles simulated using one-dimensional lattice models considering the disorder in bond polarizability arrangement.

Abstract: Lateral MOSFET devices with varying size from a single unit cell to 3x3 mm2 containing 1980 unit cells have been realised using two basic technologies; lateral trench MOSFET (LTMOS) with epitaxially grown source and drain, and lateral MOSFET with lightly doped drain (LDDMOS) having implanted source and drain regions. The LDDMOS devices had blocking capability of 100 V and the channel mobility in the range of 10 cm2/Vs in {-110} current flow direction and of 5 cm2/Vs in {110} current flow direction. The properties of both fabricated MOSFET types, LTMOS and LDDMOS, are dominated by a high density of interface states of the order of 1×1013 cm-2eV-1. Both the drain current and the leakage current scale linearly with the device size up to the maximum investigated device size of 3x3 mm2. No size limiting defects have been observed contrary to what is often the case in 4H-SiC material.

Abstract: Temperature-dependent Hall effect investigations in the channel of lateral 3C-SiC LDDMOSFETs with nitrogen(N)-implanted source/drain regions are conducted. The free electron concentration and the electron Hall mobility are independently determined. A maximum electron Hall mobility of 75 cm2/Vs is observed. The gate oxide withstands electric field strengths up to 5 MV/cm. A high density of interface states of a few 1013 cm-2eV-1 close to the 3C-SiC conduction band edge still lowers the performance of the MOS device.