Papers by Author: James Snow

Abstract: Since silicon will ultimately face physical limitations, germanium and III-V materials, such as Ga, GaAs, InGaAs, are being extensively investigated for their high electron and hole mobility advantages. Prior to implementing germanium or III-V materials, it is believed that SiGe with high Ge concentration will be applied for channel materials in pMOS devices with high-k and metal gates in order to simultaneously adjust the work function and to increase the hole mobility. However, introduction of new channel materials leads to new challenges and substantial changes in the FEOL process flow.

Abstract: The introduction of metal gates and high-k dielectrics in FEOL and porous ULK dielectrics in BEOL presents severe issues [1] and leads to the requirement of new chemistries and processes. A major challenge in cleaning is the removal of photoresist (PR) in both FEOL and BEOL. In current semiconductor device fabrication flow, the photoresist strip process in FEOL is mostly achieved by applying a sequence of plasma ashing followed by a wet-clean step with sulfuric-peroxide mixture (SPM). But in general, ashing leads to strong oxidation or etching of silicon substrate. Hence, several approaches for ashless PR strip have been reported, such as hot SPM [2] and the combination of a pre-treatment using high velocity CO2 aerosol [3].

Abstract: High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.

Abstract: Strained silicon engineering was first used at the 90-nm node. Nowadays, a series of techniques has seen wide-spread use and many derivatives are available because of their ease of integration and cost-effective features [ , ]. As a main part of stressor technique, embedded SiGe-S/D technology is reported to improve the pMOSFET drive current [ , ].

Abstract: Cleaning of nano-particles is becoming a major challenge in semiconductor manufacturing as efficient particle removal must be achieved without substrate loss and without damage to fragile structures. In this work cleaning performance and structural damage by a mixed fluid-jet technique were evaluated and directly compared to the performance of several megasonic systems. The test vehicles were hydrophilic Si wafers contaminated with 78-nm SiO2 particles and 70-nm poly-gatestack line patterned wafers. The results showed a broader process window for particle removal without damaging for the mixed fluid-jet technique compared to the megasonic systems.

Abstract: With the continuous shrinkage of critical sizes in semiconductor manufacturing, nano-particles smaller than 100-nm are becoming a potential threat to devices in chips. Storage of wafers contaminated during process steps often results in a decrease of particle removal efficiency in subsequent clean, a phenomenon referred to as aging. In this work, the influence of aging on the removal of silica and silicon nitride nano-particles from hydrophilic Si wafers was studied for different storage conditions. Trends observed for aging as a function of particle size and for different tools indicated that aging will become an issue for critical cleans where substrate etching must be kept very low and the physical component of the clean must be decreased to prevent damage to fine structures. Controlling the relative humidity during storage helped in lowering the effect of aging.

Abstract: In this work the removal of different metallic and particulate contaminants relevant for high-k/metal gate processing is studied. Best cleaning efficiency of both silicon and nitride substrates is achieved using a HF/HNO3-based cleaning resulting in a particle removal efficiency higher than 90% and metal removal down to 1010 at/cm2.