Papers by Author: Janna R. B. Casady

Abstract: In this work we present the epitaxial growth of 4H-SiC on 100mm 4° off-axis substrates grown in a multi-wafer CVD planetary reactor. Highly uniform epitaxial layers having thickness and doping uniformities of 1.7% and 1.4% respectively were grown in the production reactor with optimized process conditions at 8µm/hr and 30µm/hr growth rates. Process optimizations resulted in epitaxial layers with surface roughness (RMS) of 0.32nm. Epitaxial layers with a thickness of 53µm grown with a 30µm/hr growth process had minimal degradation in surface roughness (RMS of 0.39nm).

Abstract: We report here an anisotropic increase in SiC bulk resistivity by annealing at 1150 °C, and discuss the implications for SiC devices. The increase in resistivity is resistivity dependent and can be (at least) partially reversed by a subsequent anneal at higher temperature. Ideal device performance is achievable with appropriate annealing steps during device processing.

Abstract: 4H Silicon Carbide (4H-SiC) has a great potential for low-loss power devices due to its superior electrical properties. However, the increase in demand for the power devices requires high quality SiC substrates and epitaxial layers. Mercury probe Capacitance Voltage (Hg CV) measurement is a well known procedure to characterize epi layers grown on SiC substrates, due to its non-destructive technique. However, careful calibration of the tool is very important for repeatable and accurate measurements. Here we present very close repeatability of Hg CV within 2.4% (standard deviation 0.7%), between different Solid State Measurements (SSM) setups compared with Ni Schottky (NiS) CV. In addition to growing uniformly doped epi layers, high surface quality of the epi layer is also needed for improved device performance. Improved process conditions resulted in a smooth epi with a surface roughness Ra 1.2 nm for a 6 µm thick epi layer. Molten Potassium Hydroxide (KOH) etching analysis also revealed a significant correlation between the surface roughness and epi defects.

Abstract: In this work we have demonstrated the high-temperature operations of 600 V/50 A 4HSiC vertical-channel junction field-effect transistors (VJFETs) with an active area of 3 mm2. Specific-on resistance (RONSP) in the linear region of a single die is less than 2.6 mW.cm2 while the drain-source current is over 50 A under a gate bias (VGS) of 3 V. A reverse blocking gain of 54 is obtained at gate bias ranging from -13 V to -23 V and drain-source leakage current (IRDS) of 200 μA. To demonstrate the use of SiC VJFETs for high-power applications, eight 3 mm2 SiC VJFETs are bonded in a high current 600-V module. RONSP in the linear region of these eight-paralleled SiC VJFETs is 2.8 mW.cm2 at room temperature and increased to 5.35 mW.cm2 at an ambient temperature of 175 °C in air, corresponding to a shift of 0.61%/°C from room temperature to 175 °C. Meanwhile, the forward current is over 360 A at room temperature and reduces to 188 A at 175 °C at drain-source bias (VDS) of 5.25 V and VGS of 3 V.

Abstract: In this work we report the most recent high-temperature long-term reliability results of the 600 V/14 A, 4H-SiC vertical-channel junction field-effect transistors (VJFETs). Two groups (A and B) devices were subjected to different thermal and electrical stresses. One device (Group A) reached 12,000 hours of continuous switching without a single failure. Four devices in Group A were thermally stressed at 250 °C over 4,670 hours in air, for which standard deviation of the specific on-resistance (RONSP) in linear region at gate bias (VGS) of 3 V were < 4.1% throughout the entire duration time. The off-state characteristics were evaluated by high temperature reverse bias (HTRB) tests. Three devices (Group A) were biased at 50% rated BVDS at 250 °C for 2,278 hours. A higher reverse bias at 80 % rated BVDS was then applied to 14 devices (group B) at 200 °C for 1,000 hours. Variations of the leakage current were negligible throughout the entire HTRB test for all tested devices.

Abstract: Trenched, vertical SiC static induction transistors (SIT) for L-band power amplification were fabricated with implanted p-n junction gates on conducting n-type 4H-SiC substrates using a self-aligned fabrication process. The self-aligned fabrication process required no critical alignments and allowed for high channel packing densities ranging from 2.9x103 to 5x103 cm/cm2. Devices were fabricated with a range of finger widths. Devices with the narrowest fingers were able to block up to 450 V with VGS = -3 V. Devices with wider fingers required higher gate voltages ranging from -10 V to -25 V to achieve similar blocking. Devices were packaged and small-signal and loadpull measurements were taken with the devices externally matched. Devices having the narrowest finger design had a small-signal power gain of over 9 dB at around 1.3 GHz. Load-pull measurements of packaged SITs with 1 cm gate periphery yielded a maximum power gain of ~ 8.2 dB at 1 GHz, VDD = 100 V, and VGS = 1.2 V. Due to the high packing density, these results translate to power densities of 22 kW/cm2.

Abstract: In this work we have demonstrated the operation of 600-V class 4H-SiC vertical-channel junction field-effect transistors (VJFETs) with 6.6-ns rise time, 7.6-ns fall time, 4.8-ns turn-on and 5.4-ns turn-off delay time at 2.5 A drain current (IDS), which corresponds to a maximum switching frequency of 41 MHz – the fastest ever reported switching of SiC JFETs to our knowledge. At IDS of 12 A, a 19.1 MHz maximum switching frequency has been also achieved. Specific on-resistance (Rsp-on) in the linear region is 2.5 m
·cm2 at VGS of 3 V. The drain current density is greater than 1410 A/cm2 at 9 V drain voltage. High-temperature operation of the 4H-SiC VJFETs has also been investigated at temperatures from 25 °C to 225 °C. Changes in the on-resistance with temperature are in the range of 0.90~1.33%/°C at zero gate bias and IDS of 50 mA. The threshold voltage becomes more negative with a negative shift of 0.096~0.105%/°C with increasing temperature.

Abstract: This paper presents SiC CVD epitaxy for MESFET fabrication in a horizontal hot-wall reactor with gas foil rotation. Excellent uniformity of < 2% for thickness and < 10% for doping has been routinely obtained for both 3x2-in. and 1x3-in. growth. The highly uniform epitaxy is maintained for the growth of a large range of doping concentrations (less than 5x1015 to greater than 1.5x1019 cm-3) and thicknesses (0.25 – 60 μm). MESFET buffer/channel structure has been characterized with SIMS measurement showing sharp interface transition. Pinch-off voltages are extracted from CV measurements over a full 2-in. wafer.