Papers by Author: Kevin Matocha

Abstract: Doubly-implanted SiC vertical MOSFETs were fabricated displaying a blocking voltage of 4.2kV and a specific on-resistance of 23 mΩ-cm2, on a 4.5mm x 2.25mm device. Design variations on smaller (1.1mm x 1.1mm) devices showed on-resistance as low as 17 mΩ-cm2 with a blocking voltage of 3.3kV. Analysis is presented of the on-resistance and temperature dependence (up to 175°C), as well as switching performance. Switching tests taken at 1000V and 6A showed turn-on and turn-off transients of approximately 20-40ns.

Abstract: The gate oxide reliability and channel mobility of carbon face (000-1) 4H Silicon Carbide (SiC) MOSFETs are investigated. Several gate oxidation processes including dry oxygen, pyrogenic steam, and nitrided oxides were investigated utilizing MOS capacitors for time dependent dielectric breakdown (TDDB), dielectric field strength, and MOSFETs for inversion layer mobility measurements. The results show the C-face can achieve reliability similar to the Si-face, however this is highly dependent on the gate oxide process. The reliability is inversely related to the field effect mobility where other research groups report that pyrogenic steam yields the highest electron mobility while this work shows it has weakest oxide in terms of dielectric strength and shortest time to failure.

Abstract: The performance of 4H-SiC power MOSFETs is limited by the less than ideal electron inversion-layer mobility due to the poor quality of the SiC-SiO2 interface. This poor interface causes several undesirable behaviors of the electrical performance of SiC MOSFETs, including: (1) strong shifts in the threshold voltage with temperature, (2) low channel mobility and (3) strong sensitivity of the mobility to the channel doping concentration. These features are explained by a high density of interface states, the high surface electric field induced in SiC inversion layers, and the combined effectsa combination of Coulomb and surface roughness scattering.

Abstract: We address the two critical challenges that currently limit the applicability of SiC MOSFETs in commercial power conversion systems: high-temperature gate oxide reliability and high total current rating. We demonstrate SiC MOSFETs with predicted gate oxide reliability of >106 hours (100 years) operating at a gate oxide electric field of 4 MV/cm at 250°C. To scale to high total currents, we develop the Power Overlay planar packaging technique to demonstrate SiC MOSFET power modules with total on-resistance as low as 7.5 m. We scale single die SiC MOSFETs to high currents, demonstrating a large area SiC MOSFET (4.5mm x 4.5 mm) with a total on-resistance of 30 m, specific on-resistance of 5 m-cm2 and blocking voltage of 1400V.

Abstract: Due to the Silicon Carbide (SiC) material’s high electric field strength, wide bandgap, and good thermal conductivity, 4H-SiC thyristors are attractive candidates for pulsed power applications. With a thinner blocking layer almost an order of magnitude smaller than its Silicon (Si) counterpart, these devices promise very fast turn-on capabilities as full conductivity modulation occurs >10 times faster than comparable silicon thyristors, low leakage currents at high junction temperatures and at high voltage, and much lower forward voltage drop at high pulse currents. Our progress on the development of large area (4mm x 4mm) SiC thyristors is presented in this paper.

Abstract: nversion layers of 4H and 6H Silicon carbide based MOS devices are characterized by Gated Hall measurements to determine the trap density close to the conduction band edge and the main scattering mechanisms that limit the mobility. MOS gated Hall structures were fabricated on 4H SiC polytype with p-type doping of 5X1015cm-3 and 2X1017cm-3. MOS Gated Hall structures were also fabricated on 6H SiC polytype with p-type doping of 7.5X1015cm-3. The gate oxide was grown thermally with N2O as a precursor followed by a NO post oxidation anneal. The inversion layer Hall mobility on the 6H SiC MOSFET sample decreased with increasing temperature from room temperature to 423K, while on the 4H SiC MOSFET samples the inversion layer mobility increased slowly. Approximately 50% of the total charge density at the interface of both 6H and 4H SiC MOSFETs was found to be trapped charge. The dominant scattering mechanism in 6H SiC MOSFETs was inferred to be phonon scattering based on the temperature dependence and theoretical estimates of the phonon limited mobility. In the case of 4H SiC, we infer that at surface roughness scattering is the dominant scattering mechanisms at high surface fields.

Abstract: Low channel mobility is one of the biggest challenges to commercializing SiC MOSFETs. Accurate mobility measurement is essential for understanding the mechanisms that lead to low mobility. The most widely used effective mobility measurements overestimate the inversion charge for devices that have high level of defects. Mobility measured by the Hall effect is more accurate; however the conventional Hall mobility measurement is tedious. In this work, we demonstrate a wafer-level Hall measurement technique, which is simple and convenient to implement. With this method, extensive study of the mobility degradation is possible.

Abstract: Reliability of the gate oxide on SiC is a pressing concern for deploying SiC MOS-based devices in real systems. While good projected oxide reliability was obtained recently under highly accelerated test conditions, indication that such projection may not be valid at lower operating fields was also reported. In this work, results from long-term TDDB stress (over 7 months) at 6 MV/cm and 300 °C on 4H-SiC MOS capacitors is reported. We confirm that lifetime projection from high-field data continues to be valid and no change in field acceleration factor is observed. The discrepancy between our results and the early prediction of poor reliability is examined.

Abstract: We have extended a magnetic resonance based study of MOS devices to include electrically detected magnetic resonance (EDMR) measurements of fully processed MOSFETs from three facilities as well as conventional electron paramagnetic resonance (EPR) resonance measurements on simple SiC/SiO2 structures. We find close similarity between the conventional EPR and the EDMR spectra.

Abstract: We explain the role of nitrogen in simultaneously increasing the inversion channel mobility and reducing the threshold voltage of SiC MOSFET. A variety of computational techniques have been used to compute the atomic scale configuration of a nitridated SiC/SiO2 interface, and the corresponding change in Fermi level, inversion channel mobility, and threshold voltage. X-ray photoelectron spectroscopy (XPS) has been used to investigate the SiC/SiO2 interface to determine the nitrogen concentrations and chemical bonding. We elucidate the physics behind improved channel mobility due to NO anneal and demonstrate that the trade-off between threshold voltage and inversion channel mobility can be correlated to the extent of nitridation.