Papers by Author: Martin Domeij

Abstract: In this work, implantation-free 4H-SiC bipolar transistors with two-zone etched-JTE and improved surface passivation are fabricated. This design provides a stable open-base breakdown voltage of 2.8 kV which is about 75% of the parallel plane breakdown voltage. The small area devices shows a maximum dc current gain of 55 at Ic=0.33 A (JC=825 A/cm2) and VCESAT = 1.05 V at Ic = 0.107 A that corresponds to a low ON-resistance of 4 mΩ•cm2. The large area device shows a maximum dc current gain of 52 at Ic = 9.36 A (JC=312 A/cm2) and VCESAT = 1.14 V at Ic = 5 A that corresponds to an ON-resistance of 6.8 mΩ•cm2. Also these devices demonstrate a negative temperature coefficient of the current gain (β=26 at 200°C) and positive temperature coefficient of the ON-resistance (RON = 10.2 mΩ•cm2).

Abstract: SiC BJTs are very attractive for high power application, but long term stability is still problematic and it could prohibit commercial production of these devices. The aim of this paper is to investigate the current gain degradation in BJTs with no significant degradation of the on-resistance. Electrical measurements and simulations have been used to characterize the behavior of the BJT during the stress test. Current gain degradation occurs, the gain drops from 58 before stress to 43 after 40 hours, and, moreover, the knee current shows fluctuations in its value during the first 20 hours. Current gain degradation has been attributed to increased interface traps or reduced lifetime in the base-emitter region or small stacking faults in the base-emitter region, while fluctuations of the knee current might be due to stacking faults in the collector region.

Abstract: Vertical epitaxial NPN SiC BJTs for 1200 V rating were fabricated. Very low collector-emitter saturation voltages VCESAT=0.5 V at IC=6 A (JC=140 A/cm2) and T=25 °C and VCESAT=1.0 V at IC=6 A and T=250 °C were measured. The common emitter current gain at IC=6 A is 71 at T=25 °C and 32 at T=250 °C, respectively. A SPICE model was developed for the BJT including the parasitic capacitances of the internal pn junctions, as well as temperature dependence of the current gain and the collector series resistance. The IC-VCE characteristics of the BJT are in good agreement with the SPICE model between 25 °C and 250 °C. Fast switching measurements were performed showing a VCE voltage fall-time of 22 ns and a VCE voltage rise-time of 11 ns.

Abstract: The current gain of 4H-SiC BJTs has been modeled using interface traps between SiC and SiO2 to describe surface recombination, by a positive temperature dependence of the carrier lifetime in the base region and by bandgap narrowing in the emitter region. The interface traps have been modeled by one single level at 1 eV above the valence band, with capture cross section of 1 × 10-15 cm2 and concentration of 2 × 1012 cm-2. The temperature behavior of SiC BJTs has been simulated and the results have been compared with measurements. An analysis of the carrier concentration has been performed in order to describe the mechanisms for fall-off of the current gain at high collector current. At room temperature high injection in the base and forward biasing of the base-collector junction occur simultaneously causing an abrupt drop of the current gain. At higher temperatures high injection in the base is alleviated by the higher ionization degree of the aluminum dopants, and then forward biasing of the base-collector junction is the only acting mechanism for the current gain fall-off at high collector current. This mechanism and the negative temperature dependence of the carrier mobility can also explain the reduction of the knee current for gain fall-off with increasing temperature. Simulations with different emitter widths have been also performed and analyzed to characterize the emitter size effect. Higher current density caused by reducing the emitter width introduces higher carrier recombination in the emitter region, leading to a reduction of the current gain.

Abstract: The mechanisms of bipolar degradation in silicon carbide BJTs are investigated and identified. Bipolar degradation occurs as result of stacking fault (SF) growth within the low-doped collector region. A stacking fault blocks vertical current transport through the collector, driving the defective region into saturation. This results in considerable drop of emitter current gain if the BJT is run at a reasonably low collector-emitter bias. The base region does not play any significant role in bipolar degradation. Long-term stress tests have shown full stability of large-area high-power BJTs under minority carrier injection conditions provided the devices are fabricated using low Basal Plane Dislocation (BPD) material. However, an approximately 20% current gain compression is observed for the first 30-60 hours of burn-in under common emitter operation, which is related to instability of surface recombination in the passive base region.

Abstract: SiC power bipolar junction transistors (BJTs), for high voltage applications, have been studied under elevated temperature and electrical stress conditions. Electroluminescence has been used to capture effects of defect motion and growth, in complete transistor structures, leading to a quantifiable degradation in the electrical performance. The observed degradation of current gain (β) and on-resistance (RON) was relatively modest and saturated after a limited stress time, resulting in stable device performance. The characteristic wavelength (450 nm) of the electroluminescence, or light emission, in the visual and near infrared (NIR) range, coupled to the shape of the defects indicates that basal plane dislocations and stacking faults are involved.

Abstract: This paper reports large active area (15 mm2) 4H-SiC BJTs with a low VCESAT=0.6 V at IC=20 A (JC=133 A/cm2) and an open-base breakdown voltage BVCEO=2.3 kV at T=25 °C. The corresponding room temperature specific on-resistance RSP-ON=4.5 mΩcm2 is to the authors knowledge the lowest reported value for a large area SiC BJT blocking more than 2 kV. The on-state and blocking characteristics were analyzed by device simulation and found to be in good agreement with measurements. Fast switching with VCE rise- and fall-times in the range of 20-30 ns was demonstrated for a 6 A 1200 V rated SiC BJT. It was concluded that high dynamic base currents are essential for fast switching to charge the BJT parasitic base-collector capacitance. In addition, 10 μs short-circuit capability with VCE=800 V was shown for the 1200 V BJT.

Abstract: In this work, the electrical performance in terms of maximum current gain, ON-resistance and blocking capability has been compared for 4H-SiC BJTs passivated with different surface passivation layers. Variation in BJT performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for PECVD deposited SiO2 which was annealed in N2O ambient at 1100 °C during 3 hours. Variations in breakdown voltage for different surface passivations were also found, and this is attributed to differences in fixed oxide charge that can affect the optimum dose of the high voltage JTE termination.

Abstract: Ion implantation for selective doping of SiC is problematic due to damage generation during the process and low activation of dopants. In SiC bipolar junction transistor (BJT) the junction termination extension (JTE) can be formed without ion implantation using instead a controlled etching into the epitaxial base. This etched JTE is advantageous because it eliminates ion implantation induced damage and the need for high temperature annealing. However, the dose, which is controlled by the etched base thickness and doping concentration, plays a crucial role. In order to find the optimum parameters, device simulations of different etched base thicknesses have been performed using the software Sentaurus Device. A surface passivation layer consisting of silicon dioxide, considering interface traps and fixed trapped charge, has been included in the analysis by simulations. Moreover a comparison with measured data for fabricated SiC BJTs has been performed.

Abstract: In this study, high voltage blocking (2.7 kV) implantation-free SiC Bipolar Junction Transistors with low on-state resistance (12 mΩ•cm2) and high common-emitter current gain of 50 have been fabricated. A graded base doping was implemented to provide a low resistive ohmic contact to the epitaxial base. This design features a fully depleted base layer close to the breakdown voltage providing an efficient epitaxial JTE without ion implantation. Eliminating all ion implantation steps in this approach is beneficial for avoiding high temperature dopant activation annealing and for avoiding generation of life-time killing defects that reduces the current gain. Also in this process large area transistors showed common-emitter current gain of 38 and open-base breakdown voltage of 2 kV.