Papers by Author: Masashi Nakabayashi

Abstract: Time-dependent evolutions of single and quadruple Shockley stacking faults (sSSF and 4SSF) in 4° off 4H-SiC epitaxial layers have been investigated. UV illuminations using an Hg-Xe lamp light source generate dissociations of basal plane dislocations (BPDs) into sSSFs whereas for 4SSFs no significant changes in shape occur. Detailed analyses of Photo-luminescence (PL) signals suggest that Si- and C-core partials have different PL spectrum distributions in the wavelength range larger than 750 nm, giving rise to images with different contrasts in PL mappings.

Abstract: Dislocations in highly nitrogen-doped (N > 1×1019 cm-3) low-resistivity ( < 10 mcm) 4H-SiC substrates were investigated by photoluminescence imaging, synchrotron X-ray topography, and defect selective etching using molten KOH. The behavior of dislocations is discussed particularly in terms of their glide motion in the presence of a high concentration of nitrogen. The results indicate that nitrogen impurities up to mid 1019 cm-3 concentration do not show any discernible influence on the glide behavior of basal plane dislocations (BPDs) in 4H-SiC crystals grown by physical vapor transport (PVT) method.

Abstract: The epitaxial growth process was optimized in order to obtain good surface morphology for epilayers grown on 4˚ off-axis substrates. The optimization was carried out from growth temperatures and gas chemistry including C/Si ratio. Step-bunching was significantly suppressed by the optimized process and a surface roughness Ra of 0.2 nm was achieved. Etch pit density evaluation by KOH etching indicated that the basal plane dislocations were reduced to less than 50 cm-2 by the use of 4˚ off-axis substrates. Photoluminescence evaluation showed that the epilayer grown by the optimized process had a better crystalline quality than that grown by a standard process. Schottky diodes fabricated on the epilayer by the optimized process represented the ideality factor n of 1.01 and the barrier height of 1.67eV. These results demonstrate that high quality epilayers with smooth surfaces comparable to those on 8˚off-axis substrates were obtained on 4˚off-axis substrates.

Abstract: In-grown type stacking faults (SFs) like structures were observed in 100mm diameter 4H-SiC crystals by Photoluminescence (PL) mappings, and structural analyses using HRTEM clarified that the SF-like structures were comprised of 6H (3, 3) stacking sequences. The stacking sequences of the SF-like structures observed are different from the SFs formed in the a-face grown crystals, suggesting that it is due to 6H nucleation on {0001} plane terraces.

Abstract: The development of lapping and polishing technologies for SiC single crystal wafers has realized the fabrication of an extremely flat SiC wafer with excellent surface quality. To improve the SiC wafer flatness, we developed a four-step lapping process consisting of four stages of both-side lapping with different grit-size abrasives. We have applied this process to lapping of 2-inch-diameter SiC wafers and obtained an excellent flatness with TTV (total thickness variation) of less than 3 μm, LTV (local thickness variation) of less than 1 μm, and SORI smaller than 10 μm. We also developed a novel MCP (mechano-chemical polishing) process for SiC wafers to obtain a damage-free smooth surface. During MCP, oxidizing agents added to colloidal silica slurry, such as NaOCl and H2O2, effectively oxidize the SiC wafer surface, and then the resulting oxides are removed by colloidal silica. AFM (atomic force microscope) observation of polished wafer surface revealed that this process allows us to have excellent surface smoothness as low as Ra=0.168 nm and RMS=0.2 nm.

Abstract: The stacking fault formation in highly nitrogen-doped n+ 4H-SiC single crystal substrates during high temperature treatment has been investigated in terms of the surface preparation conditions of substrates. Substrates with a relatively large surface roughness showed a resistivity increase after annealing at 1100°C, which was confirmed to be caused by the formation and expansion of double Shockley-type basal plane stacking faults in the substrates. The occurrence of the stacking faults largely depended on the surface preparation conditions of the substrates, which indicates that the primary nucleation sites of stacking faults exist in the near-surface regions of substrates. In this regard, mechano-chemically polished (MCP) substrates with a minimum surface roughness (< 0.3 nm) exhibited no resistivity increase and very few stacking faults after annealing even when the nitrogen concentration of the substrates exceeded 1×1019 cm-3.

Abstract: The theromoelastic stress in post-growth SiC crystals has been investigated in order to suppress the cracks which were frequently observed in SiC crystals with larger diameters. Optimizing the temperature distribution in growing crystals lead to reduction of tensile stress components, and thus resulting in crack-free 100mm diameter SiC crystals with micropipe (MP) densities of 0.025/cm2. The concept of process optimization we established is confirmed to be effective to the growth of large diameter SiC crystals with mechanical stability.

Abstract: The coefficient of thermal expansion (CTE) of SiC single crystals is important, in particular, for both designing device assembly and controlling stress distributions in heteroepitaxial thin film structures grown onto SiC substrates. We have performed very precise measurements of the CTEs for SiC single crystals comprising of single 4H polytype PVT-grown in NIPPON Steel Corporation for a temperature range from 123 K to 473 K using a laser interferometry method. This method allows us to directly measure the temperature dependent variation in thermal expansion of the crystal volume with much higher accuracy, and enables us to straightforwardly obtain practical information of CTE data. Furthermore in order to discuss the CTE behavior for a wider temperature range the CTEs at higher temperatures up to 1573 K have been also measured using dilatometer method. The CTE obtained for a nitrogen-doped 4H-SiC single crystal increases continuously from 0.8 ppm/K to 3.1 ppm/K for temperatures of 273 K and 423 K respectively, and further increases to 5.4 ppm/K at 1273 K. We conclude from our data that the CTE variations are likely to be almost independent of the crystal axis directions of SiC from 123 K up to 1573 K.

Abstract: 4H-SiC epitaxial layers on Carbon-face (C-face) substrates were grown by a low-pressure hot-wall type chemical vapor deposition system. The C-face substrates were prepared by fine mechanical polishing using diamond abrasives with the grit size of 0.25 %m and in-situ HCl etching at 1400°C, which produced surface roughness of 0.27 nm. The use of the smooth substrates made it possible to decrease the substrate temperature and specular surface morphologies were realized at C/Si ratios of 1.5 or less both for a substrate temperature of 1550°C and for that of 1500°C. Surface roughness of 0.26 nm and the residual donor concentration of 6.7×1014 cm-3 were obtained for a C-face epitaxial layer grown at a C/Si ratio of 1.5 and at a substrate temperature of 1550°C. Schottky barrier diodes were fabricated on a non-doped C-face epitaxial layer grown at 1500°C and it was verified that a high quality metal-semiconductor interface was formed on the epitaxial layer.