Papers by Author: Michael J. Paisley

Abstract: Availability of high-quality, large diameter SiC wafers in quantity has bolstered the commercial application of and interest in both SiC- and nitride-based device technologies. Successful development of SiC devices requires low defect densities, which have been achieved only through significant advances in substrate and epitaxial layer quality. Cree has established viable materials technologies to attain these qualities on production wafers and further developments are imminent. Zero micropipe (ZMP) 100 mm 4HN-SiC substrates are commercially available and 1c dislocations densities were reduced to values as low as 175 cm-2. On these low defect substrates we have achieved repeatable production of thick epitaxial layers with defect densities of less than 1 cm-2 and as low as 0.2 cm-2. These accomplishments rely on precise monitoring of both material and manufacturing induced defects. Selective etch techniques and an optical surface analyzer is used to inspect these defects on our wafers. Results were verified by optical microscopy and x-ray topography.

Abstract: DC characteristics and reverse recovery performance of 4H-SiC Junction Barrier Schottky (JBS) diodes capable of blocking in excess of 10 kV with forward conduction of 20 A at a forward voltage of less than 4 V are described. Performance comparisons are made to a similarly rated 10 kV 4H-SiC PiN diode. The JBS diodes show a significant improvement in reverse recovery stored charge as compared to PiN diodes, showing half of the stored charge at 25°C and a quarter of the stored charge at 125°C when switched to 3 kV blocking. These large area JBS diodes were also employed to demonstrate the tremendous advances that have recently been made in 4H-SiC substrate quality.

Abstract: Recent advances in PVT c-axis growth process have shown a path for eliminating micropipes in 4HN-SiC, leading to the demonstration of zero micropipe density 100 mm 4HN-SiC wafers. Combined techniques of KOH etching and cross-polarizer inspections were used to confirm the absence of micropipes. Crystal growth studies for 3-inch material with similar processes have demonstrated a 1c screw dislocation median density of 175 cm-2, compared to typical densities of 2x103 to 4x103 cm-2 in current production wafers. These values were obtained through optical scanning analyzer methods and verified by x-ray topography.

Abstract: Structure of the “carrot” defects in 4H-SiC homoepitaxial layers deposited by CVD has been investigated by plan-view and cross-sectional transmission x-ray topography, cross-sectional transmission electron microscopy, atomic force microscopy, and KOH etching. The carrot defects nucleate at the substrate/epilayer interface at the emergence points of threading screw dislocations propagating from the substrate. The typical defect consists of two stacking faults: one in the prismatic plane with second one in the basal plane. The faults are connected by a stair-rod dislocation with Burgers vector 1/n[10-10] with n>3 at the cross-over. The basal plane fault is of Frank-type. Carrot defects are electrically active as evidenced by contrast in EBIC images indicating enhanced carrier recombination rate. Presence of carrot defects in the p-i-n diodes results in higher pre-breakdown reverse leakage current and approximately 50% lower breakdown voltage compared to the nominal value.

Abstract: Experimental results are presented for SiC epitaxial layer growth employing a large-area, up to 8x100-mm, warm-wall planetary SiC-VPE reactor. This high-throughput reactor has been optimized for the growth of uniform 0.01 to 80-micron thick, specular, device-quality SiC epitaxial layers with low background doping concentrations of <1x1014 cm-3 and intentional p- and n-type doping from ~1x1015 cm-3 to >1x1019 cm-3. Intrawafer layer thickness and n-type doping uniformity (σ/mean) of ~2% and ~8% have been achieved to date in the 8x100-mm configuration. The total range of the average intrawafer thickness and doping within a run are approximately ±1% and ±6% respectively.

Abstract: Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.

Abstract: We present a survey of the most important factors relating to an epitaxial SiC growth process that is suitable for bipolar power devices. During the last several years, we have advanced our hot-wall SiC epitaxial growth technology to the point that we can support the transition of bipolar power devices from demonstrations to applications. Two major concerns in developing a suitable epitaxial technology are epilayer uniformity and extended defect density. Our state-of-theart capability permits the realization of 1-cm2 area devices with exceptional yields. Another major concern is the stability of bipolar devices during forward conduction. We have developed proprietary substrate and epilayer preparation technologies that have essentially eliminated Vf drift as a significant barrier to the exploitation of SiC based bipolar devices.

Abstract: Experimental results are presented for SiC epitaxial layer growths employing a largearea, 7x3-inch, warm-wall planetary SiC-VPE reactor. This high-throughput reactor has been optimized for the growth of uniform 0.01 to 30-micron thick, specular, device-quality SiC epitaxial layers with background doping concentrations of <1x1014 cm-3. Multi-layer device profiles such as Schottky, MESFETs, SITs, and BJTs with n-type doping from ~1x1015 cm-3 to >1x1019 cm-3, p-type doping from ~3x1015 cm-3 to >1x1020 cm-3, and abrupt doping transitions (~1 decade/nm) are regularly grown in continuous growth runs. Intrawafer layer thickness and n-type doping uniformities of <1% and <5% s/mean have been achieved. Within a run, wafer-to-wafer thickness and doping variation are ~±1% and ~±5% respectively. Long term run-to-run variations while under process control are approximately ~3% s/mean for thickness and ~5% s/mean for doping. Latest results from an even larger 6x4-inch (100-mm) reactor are also presented.