Papers by Keyword: Static Induction Transistor

Abstract: The process technology for the fabrication of 4H-SiC Static Induction Transistors (SITs) has been developed. Conventional contact UV lithography and self-aligned techniques have been employed. Al-outdiffusion following Rapid Thermal Annealing (RTA) has been determined as the cause for the increased reverse leakage and early forward turn-on of the gate-source junction. The fabricated transistors, exhibited a specific R_ON value in the region of 2mΩ•cm² and 80 V turn-off voltage.

Abstract: In this study, we evaluated the radiation hardness of SiC Buried Gate Static Induction Transistors (SiC-BGSITs) and Si-based switching devices up to the absorbed dose of 10 MGy(SiO2). The on-voltage Von of Si-IGBT degraded excessively at the early stage of the irradiation (>~0.1 MGy(SiO2)) due to the bulk damage produced by Compton electrons like the gain degradation in Si bipolar transistors. The threshold voltage Vth of Si-MOSFET was very sensitive against the radiation due to the competing mechanism between the generation of the hole traps in the gate SiO2 and the SiO2/Si interface states. Moreover, the breakdown voltage VBR and leak current Ileak of MOSFET degraded significantly against the absorbed dose. While, the electrical properties of SiC-BGSIT was very stable even after the irradiation of 10 MGy(SiO2).

Abstract: Since SiC VJFETs are believed to offer extremely fast turn on and turn off processes it is important to understand how these transients are tailored by the layout. Regarding the basic layouts two main topologies are under investigation today – structures with the well known SIT layout with purely vertical current flow and lateral vertical concepts where the current flow through the channel is in lateral direction and the vertical current flow takes place in the drift region only. In this paper we will focus on differences in the electric characteristics of both structures and the relation of the dynamic behavior to the topology and the layout of the switches. For the analysis, 1200V VJFETs based on the two basic topologies were manufactured having approximately the same total and active device area. It turns out that the SIT switches under investigation suffer from a high internal gate resistance in the p-doped layers and a relatively high gate drain capacitance.

Abstract: We investigated the crystalline quality and electrical properties of the channel regions in 4H-SiC buried gate static induction transistors (SiC-BGSITs). To accurately determine the characteristics of the channel regions, we performed transmission electron microscopy and scanning spreading resistance microscopy. It was found that the channel regions have high crystalline quality and no significant fluctuations in doping concentration.

Abstract: Short-circuit capabilities of silicon carbide static induction transistors with the buried gate structures (BGSITs) have been measured for the first time, and have been followed by 2D device simulations. The short-circuit operation of the normally-on type BGSITs is characterized by an abrupt decrease in the output current through a high peak in the initial phase of the short-circuit period, which is distinguished from that of the conventional IGBTs and power MOSFETs. This operation is caused by the inherent operation of the SITs including the non-saturating current-voltage characteristics with the unipolar operation. Decreasing the channel width adequately is a useful method to increase the short-circuit capability.

Abstract: The turnoff mechanism of SiC buried gate static induction transistors (SiC-BGSITs) were analyzed by three dimensional device simulation. A current crowding occurs in the portion near the channel center away from the gate contact during the initial phase of the turnoff operation, which is resulted from a non-uniform potential distribution through the gate finger with the displacement current flowing there. This increases the turnoff delay time. The impact of source length on the turnoff performance was made clear.

Abstract: Trenched, vertical SiC static induction transistors (SIT) for L-band power amplification were fabricated with implanted p-n junction gates on conducting n-type 4H-SiC substrates using a self-aligned fabrication process. The self-aligned fabrication process required no critical alignments and allowed for high channel packing densities ranging from 2.9x103 to 5x103 cm/cm2. Devices were fabricated with a range of finger widths. Devices with the narrowest fingers were able to block up to 450 V with VGS = -3 V. Devices with wider fingers required higher gate voltages ranging from -10 V to -25 V to achieve similar blocking. Devices were packaged and small-signal and loadpull measurements were taken with the devices externally matched. Devices having the narrowest finger design had a small-signal power gain of over 9 dB at around 1.3 GHz. Load-pull measurements of packaged SITs with 1 cm gate periphery yielded a maximum power gain of ~ 8.2 dB at 1 GHz, VDD = 100 V, and VGS = 1.2 V. Due to the high packing density, these results translate to power densities of 22 kW/cm2.