Papers by Keyword: (11-20)

Abstract: We have fabricated the lateral MOSFETs on (11-20) and (1-100) faces and have compared the properties between these faces with various gate oxide processes. It has been demonstrated that (11-20) and (1-100) faces show comparable electrical properties with nitridation treatment on the gate oxide. Our result indicates that both faces exhibit the similar trend of the mobility vs. D_it. Furthermore, it has been shown that NO POA is beneficial to both faces in achieving high channel mobility and suppressed V_t instability.

Abstract: We have studied gate oxide processes for SiC trench MOSFETs. It is demonstrated that nitridation of gate oxide is effective to suppress the variation of channel mobility depending on channel plane orientation and substrate off-angles. In addition, improved channel mobility has been obtained by the combined process of NH₃ and N₂O POA.

Abstract: We report on the fabrication and testing of SiC p-i-n avalanche photodiodes. APDs of 0.25 mm2 area on a-plane (1120) 6H-SiC as well as off-axis Si face 6H and 4H-SiC were successfully fabricated. A beveled mesa was used as edge termination. Recessed windows were formed using reactive ion etching to enhance low-wavelength UV performance. We performed current-voltage tests with and without UV illumination to determine dark current, photocurrent, and gain on selected devices. Dark current was less than 1 pA at 0.5Vbr on multiple devices. Quantum efficiency of 40% or greater was observed for all orientations and polytypes.

Abstract: Ab initio calculations were carried out to study the origin of the trap at the SiO2/SiC (MOS: Metal-Oxide-Semiconductor) interface with the three different faces of the substrate, (0001), (000-1), and (11-20). In a previous report we experimentally discovered that the (11-20) face is suitable for high channel mobility. The calculation in this report showed that the MOS interface achieved the intermediate states due to distortion and thus acted like an interface trap. The interface trap density of the MOS interface on the (11-20) face substrate was smaller than those on the other faces. The interface trap densities were 2.14, 3.36, and 1.40 in units of 1015 cm-2 for the above listed substrate orientations, respectively. For clarity, the channel mobility was compared experimentally to reveal that it realized a larger value for the (11-20) substrate than the other two faces. From our results, we concluded that (11-20) face substrate was more suitable for high power device applications than the (0001) face or (000-1) face substrates.

Abstract: P-channel MOSFETs have been fabricated on 4H-SiC (0001) face as well as on 4H-SiC (03-38) and (11-20) faces. The gate oxides were formed by thermal oxidation in dry N2O ambient, which is widely accepted to improve the performance of n-channel SiC MOSFETs. The p-channel SiC MOSFETs with N2O-grown oxides on 4H-SiC (0001), (03-38), and (11-20) faces show a channel mobility of 7 cm2/Vs, 11 cm2/Vs, and 17 cm2/Vs, respectively. From the quasi-static C-V curves measured by using gate-controlled diodes, the interface state density was calculated by an original method. The interface state density was the lowest at the SiO2/4H-SiC (03-38) interface (about 1x1012 cm-2eV-1 at EV + 0.2 eV). The authors have applied deposited oxides to the 4H-SiC p-channel MOSFETs. The (0001), (03-38), and (11-20) MOSFETs with deposited oxides exhibit a channel mobility of 10 cm2/Vs, 13 cm2/Vs, and 17 cm2/Vs, respectively. The deposited oxides are one of effective approaches to improve both n-channel and p-channel 4H-SiC MOS devices.

Abstract: The effect of using different orientations of 4H-SiC substrates on the performance of 4H-SiC MOSFETs has been evaluated. Three sets of samples with (0001), (000-1) and (11-20) oriented SiC substrates were used to fabricate the MOSFETs, with a gate oxide process consisting of a low- temperature deposited oxide followed by NO anneal at 1175°C for 2hrs. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted. Temperature characterization up to 225°C was also performed.

Abstract: 4H-SiC (0001) MOSFETs with a three-dimensional gate structure, which has a top channel on the (0001) face and side-wall channels on the {11-20} face have been fabricated. The three-dimensional gate structures with a 1-5 m width and 0.8 m height have been formed by reactive ion etching, and the gate oxide has been deposited by plasma-enhanced chemical vapor deposition and then annealed in N2O ambient at 1300°C. The fabricated MOSFETs have exhibited superior characteristics: ION / IOFF, the subthreshold swing and VTH are 1010, 250 mV/decade and 3.5 V, respectively. The drain current normalized by the gate width is increasing with decreasing the gate width. The normalized drain current of a 1 m-wide MOSFET is ten times higher than that of a conventional planar MOSFET.

Abstract: We have investigated the techniques to improve the channel mobility of SiC MOSFETs and found that the hydrogen termination of dangling bonds at a MOS interface is very effective in improving the channel mobility, particularly that of the interface fabricated on a (11-20) face wafer. A high channel mobility of MOSFET on the (11-20) face was achieved to 244cm2/Vs by new process which can terminate dangling bonds by hydrogen. The vertical MOSFET, which is prepared using this process, has a low on-resistance of 5.7 mΩcm2 and a breakdown voltage of 1100 V. The channel resistance is estimated at 0.58 mΩcm2.

Abstract: Anisotropic thermal etching of 4H-SiC {0001} and {11-20} substrates was studied in the mixed gas of chlorine (Cl2) and oxygen (O2) over 900oC. Etch pits appeared only on the (0001) Si face. Etching rates depended on the temperature, O2/Cl2 ratio, and an etching direction on the substrate surfaces. When the mesa structure was formed by the selective etching method, sloped sidewalls were observed around the periphery of the mesa. The angle of sidewalls depended on the orientation of substrates.

Abstract: This paper reports the channel mobilities of MOSFETs formed on the trench sidewalls with different crystal faces including (0001), (000-1), (1-100) and (0-33-8) using 4H-SiC (11-20) substrates. Deposited poly-Si was oxidized in wet ambient to form the gate oxide, and annealed in N2O (10%) ambient. The order of drain current of trench sidewall MOSFETs was (0-33-8) > (1-100) > (000-1) = (0001). We could gain comparatively high channel mobility on the (0-33-8) face. The maximum effective channel mobility (μeff) was 35cm2/Vs, and μeff at 2.5MV/cm was 29 cm2/Vs on the (0-33-8) face.