Analytical Modeling for Short Channel SOI-MOSFET and to Study its Performance

Abstract:

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With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.

Info:

Periodical:

Edited by:

Wu Fan

Pages:

5150-5154

DOI:

10.4028/www.scientific.net/AMM.110-116.5150

Citation:

K. S. Kumar et al., "Analytical Modeling for Short Channel SOI-MOSFET and to Study its Performance", Applied Mechanics and Materials, Vols. 110-116, pp. 5150-5154, 2012

Online since:

October 2011

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$35.00

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