A Novel Comparator Circuit of Single-Electron and MOS Transistors

Abstract:

A novel combination of single-electron transistors (SET) with MOS transistors is advanced to create inverter, which, compared with the pure SET circuit, is considerably augmented in its voltage gain and drive capability. Then a close analysis was conducted of the inverter, on the basis of which other logic gates were presented, thus achieving a circuit of two-bit digital comparator. The accuracy of the circuit is verified through the test on SPICE. This hybrid circuit shares the merits with both SET circuit and MOS circuit. Compared with the traditional circuits, this one uses fewer electronic components and is lower in power depletion.

• Periodical: Applied Mechanics and Materials (Volume 120)
• Pages: 516-519
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.120.516
• Online since: October 2011
• Authors: You Jie Zhou, Chun Hua Xiong, Chang Bo Lu
• Keywords: Digital Comparator, Inverter, MOS Transistor, SPICE

References

[1] Single electron transistors. http://www.mcuwork.com/data/2007/0214/article_19594.htm

[2] C. Wasshuber , "Computational Single Electronics" [M]. New York: Springer Verlag , 2001.

[3] Wancheng Zhang, Nan-Jian Wu, Tamotsu Hashizume, "Novel Hybrid Voltage Controlled Ring Oscillators Using Single Electron and MOS Transistors," IEEE Trans. on Nanotechnology, Vol. 6(2): pp.170-175, Mar. 2007.

DOI: 10.1109/tnano.2007.891817

[4] Kyu-Sul Park, Sang-Jin Kim, In-Bok Baek etal., "SOI Single-Electron Transistor With Low RC Delay for Logic Cells and SET/FET Hybrid ICs" .IEEE, Trans. on Nanotechnology, Vol. 4(2): pp.242-248, Mar. 2005.

DOI: 10.1109/tnano.2004.837857

[5] S.Mahappatra, Adrian Mihai Ionescu, "Realization of Multiple Valued Logic and Memory by Hybrid SETMOS Architecture", IEEE, Trans. on Nanotechnology,Vol. 4(6): pp.705-714,Nov.2005.

DOI: 10.1109/tnano.2005.858602

[6] H. Inokawa, A. Fujiwara, and Y.Takahashi,"A multiple-valued logic and memory with combined single-electron and metal-oxide-semi-conductor transistors," IEEE Trans. Electron Devices, vol. 50, no. 2, p.462–470, Feb. 2003.

DOI: 10.1109/ted.2002.808421

[7] Santanu Mahapatra and Adrian Mihai lonescu. Hybrid CMOS-Single Electron Transistor Device and Circuit Design [M]. London: Artech House,2006.

[8] Santanu Mahapatra, Vaibhav Vaish, Christoph Wasshuber etal., "Analytical Modeling of Single Electron Transistor for Hybrid CMOS-SET Analog IC Design", IEEE,Vol. 51 (11): p.1772~1781, 2004.

DOI: 10.1109/ted.2004.837369

[9] Dae Hwan Kim, Suk-Kang Sung, Kyung Rok Kim etal., "Single-Electron Transistors Based on Gate-Induced Si Island for Single-Electron Logic Application", IEEE Trans. on Nanotechnology, Vol. 1(4): pp.170-175. December 2002.

DOI: 10.1109/tnano.2002.807382

[10] Liu Hechao, Cai Li, WangSen, "A Comparator Based on Multi-gate Single-Electron Transistors" [J], Microelectronics, Vol. 35(1): pp.59-62. 2005.

[11] Huaguang Kang. Electron technology foundation (digital part)[M].Higher Education Press, China, 2000:P151.