FPGA-Based Design of Resource-Efficient Digital down Converter

Shu Lin Cui; Xu Li

doi:10.4028/www.scientific.net/AMM.128-129.878

Paper Titles

Failure Modes and Countermeasures of Working Device of a Heavy Vehicle
p.859

Fault Diagnosis of CNC Machine Using Hybrid Neural Network
p.865

Fault Diagnosis of Power Quality
p.870

Flipping PTS-OFDM System without Side Information
p.874

FPGA-Based Design of Resource-Efficient Digital down Converter
p.878

Fuzzy Control System of Titanium Dioxide Hydrolysis Process
p.882

Fuzzy Depth Control of Small Cylindrical Object Navigating near Free-Surface
p.886

Fuzzy Immune PID Control for 6-DOF Parallel Platform
p.890

H_∞ Control of Flexible Joint Robot via T-S Fuzzy Model
p.894

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 128-129FPGA-Based Design of Resource-Efficient Digital...

FPGA-Based Design of Resource-Efficient Digital down Converter

Abstract:

Digital down converter (DDC) is based on the theory of Software Defined Radio (SDR) and multirate signal processing, extensively applied in digital receivers of communications systems. An improved resource-efficient DDC with polyphase architecture and distributed arithmetic (DA) is presented in this paper. The design based on Xilinx FPGA Virtex-5 has more flexible characters and higher precision computation with less resource consumption.

You might also be interested in these eBooks

Measuring Technology and Mechatronics Automation IV

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volumes 128-129)

Pages:

878-881

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.128-129.878

Citation:

Cite this paper

Online since:

October 2011

Authors:

Shu Lin Cui, Xu Li

Keywords:

DDC, Distributed Arithmetic, Field-Programmable Gate Array (FPGA), Polyphase Structure

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

References

[1] Qing Wang, Songbai He, Ziming Zhong, in: Design and Simulation of an Optimized DDS, Wireless Communications Networking and Mobile Computing (WiCOM), pp.1-3, Sept. (2010).

Google Scholar

[2] Wu Changrui, Kong Chao, Xie Shigen, in: Design and FPGA Implementation of Flexible and Efficiency Digital Down Converter, Signal Processing (ICSP), pp.438-441, Oct, (2010).

DOI: 10.1109/icosp.2010.5654948

Google Scholar

[3] Hua-Ming Liu, Guang-Jun Li, Bo Yan and Qiang Li, in: A 100MHz Digital Down Converter wit Modified FIR Filter for Wideband Software-Defined Radios, Electronics and Information Engineering (ICEIE), vol. 2, pp.540-544, Aug. (2010).

DOI: 10.1109/iceie.2010.5559748

Google Scholar

[4] Xu, X., Xie, X., Wang, F., in: Digital Up and Down Converter in IEEE 802. 16d [J], Signal Processing, vol. 1, (2006).

Google Scholar

[5] Bai Fengming, Lv Xiaoli, in: Programming design of Digital Down Converter based on software radio, Circuits, Communications and System, vol. 1, pp.351-354,. (2010).

DOI: 10.1109/paccs.2010.5626883

Google Scholar