Research on Cipher Coprocessor Instruction Level Parallelism Compiler

Hong Yan Li

doi:10.4028/www.scientific.net/AMM.130-134.2907

Paper Titles

The Research of Multipath and Linear Error for Pseudolites Applications
p.2890

Quadrilateral Grid Automatic Generation Algorithm and its Application for Multi-Media and Complex Domain
p.2895

The Research on Hadoop and Cloud Computing-Based Mass Data Storage Model of Computation
p.2899

Reconfigurable Design and Implementation of Data Extraction and Permutation Facing Stream Cipher Algorithm
p.2903

Research on Cipher Coprocessor Instruction Level Parallelism Compiler
p.2907

A New Image Affine-Invariant Region Detector and Descriptor
p.2911

Dimension-Descending Algorithm for Spherical Delaunay Triangulation
p.2915

Ergonomics Evaluation of Mobile Maintenance Shelter with Fuzzy AHP Method
p.2920

Performing Calculation in Interactive Theorem Proving
p.2924

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 130-134Research on Cipher Coprocessor Instruction Level...

Research on Cipher Coprocessor Instruction Level Parallelism Compiler

Abstract:

The important method of studying cipher coprocessor is focus on system architecture of processor in combination with reconfigurable design technique. How to improve performance of cipher coprocessor is important. Based on very long instruction word (VLIW) structure and reconfigurable design technique, specific instruction cipher coprocessor is designed. In this paper, the cipher coprocessor instruction level parallelism compilation technique is studied to enhance the cipher coprocessor performance by increasing the instruction level parallelism.

You might also be interested in these eBooks

Mechanical and Electronics Engineering III

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volumes 130-134)

Pages:

2907-2910

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.130-134.2907

Citation:

Cite this paper

Online since:

October 2011

Authors:

Hong Yan Li

Keywords:

Cipher Coprocessor, Instruction Scheduling Reconfigurable Computing, Very Long Instruction Word (VLIW)

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

References

[1] LAM，MONICA S．Instructions Scheduling for Superscalar Architectures，in Joseph F．Traub（ed．）．Annual Review of Comp．Sci．，Vol．4，Annual Reviews，Inc．，Palo Alto，CA， pp．173-201(1990).

Google Scholar

[2] LAM，MONICA S．Software Pipelining：An Efficient Scheduling Technique for VLIW Machines，in [PLDI88]，pp．318-328.

Google Scholar

[3] JAIN，SUNIL．Circular Scheduling：A New Technique to Perform Software Pipelining，in [PLDI91]，pp．219-228.

Google Scholar

[4] BODIN，FRANCOIS and FRANCOIS CHAROT．Loop Optimization for Horizontal Microcoded Machines，proc．Of the 1990 Intl．Conf．on Supercomputing，Amsterdam， pp．164-176 (1990).

Google Scholar

[5] EISENBEIS，CHRISTINE and D．WINDHEISER．A New Class of Algorithms for Software Pipelining with Resource Constraints，Tech．Pept．，INRIA，Le Chesnay，France{1992}.

Google Scholar