Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems

Article Preview

Abstract:

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

You might also be interested in these eBooks

Info:

Periodical:

Pages:

469-473

Citation:

Online since:

October 2012

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2012 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

[1] Benjamin J. Patella, Aleksandar Prodic: High-frequency digital PWM controller IC for DC–DC converters, IEEE Trans. Power Electronics, vol. 18, no. 1, (2003), p.438–446.

DOI: 10.1109/tpel.2002.807121

Google Scholar

[2] S. Nonaka and Y. Neba: Single phase composit PWM voltage source converter, IEEE IAS, (1994), pp.761-767.

DOI: 10.1109/ias.1994.377504

Google Scholar

[3] K. Nielsen: A review and comparison of pulse width modulation (PWM) methods for analog and digital input switching power amplifiers, presented at the 102nd Conv. AES, Munich, Germany, Paprint 4446. (1997).

Google Scholar

[4] E. C. Dijkmans and J. A. T. M. van den Homberg: PWM amplifier with feedback loop integrator, U.S. Patent 6 300 825. (2001).

Google Scholar

[5] Ali Hajimiri, Sotirios Limotyrakis, and Thomas H. Lee: Jitter and phase noise in ring oscillators, IEEE J. Solid–State Circuits, vol. 36, no. 6, (1999), p.790–804.

DOI: 10.1109/4.766813

Google Scholar

[6] Udo Karthaus and Stefan Schabel: Write pulse generator for 16x DVD recording with symmetric CMOS inverter ring oscillator, IEEE J. Solid–State Circuits, vol. 40, no. 11, (2005), p.2286–2295.

DOI: 10.1109/jssc.2005.857373

Google Scholar

[7] Manop Thamsirianunt and Tadeusz A. Kwasniewski: CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications, IEEE J. Solid–State Circuits, vol. 32, no. 10, (1997) p.1511–1524.

DOI: 10.1109/4.634659

Google Scholar

[8] J. Mahattanakul: Design procedure for two-stage CMOS operational amplifiers employing current buffer, IEEE Trans. Circuits Syst. II: Express Briefs, vol. 52, no. 11, (2005), p.766–770.

DOI: 10.1109/tcsii.2005.852530

Google Scholar

[9] Girish Kurkure and Aloke K. Dutta: A novel adaptive biasing scheme for CMOS Op-Amps, J. Semiconductor Technology and Science, vol. 5, no. 3, (2005), p.168–172.

Google Scholar

[10] Maria del Mar Hershenson, Stephen P. Boyd: and Thomas H. Lee, Optimal design of a CMOS Op-Amp via geometric programming, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 1, (2001), p.1–21.

DOI: 10.1109/43.905671

Google Scholar

[11] John K. Fiorenza, Todd Sepke, Peter Holloway: Charles G. Sodini, and Hae-Seung Lee, Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies, IEEE J. Solid–State Circuits, vol. 41, no. 12, (2006), p.2658–2668.

DOI: 10.1109/isscc.2006.1696121

Google Scholar