Efficient Hardware Architecture for Kernel Fuzzy C-Means Algorithm

Chien Min Ou; Wen Jyi Hwang; Ssu Min Yang

doi:10.4028/www.scientific.net/AMM.284-287.3079

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Combined Probabilistic and Possibilistic Used to a Build Type-2 Fuzzy Clustering Algorithm Model
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Data Mining Based Intelligent System for Voting Behavior Analysis
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Detection of Content-Aware Image Resizing Using Seam Properties
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Efficient Hardware Architecture for Kernel Fuzzy C-Means Algorithm
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Estimation of Distribution Algorithms with Matrix Transpose in Bayesian Learning
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Fast Depth Generating Algorithm From Binocular Images
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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 284-287Efficient Hardware Architecture for Kernel Fuzzy...

Efficient Hardware Architecture for Kernel Fuzzy C-Means Algorithm

Abstract:

A novel VLSI architecture for kernel fuzzy c-means algorithm is presented in this paper. The architecture consists of efficient circuits for the computation of kernel functions, membership coefficients and cluster centers. In addition, the usual iterative operations for updating the membership matrix and cluster centers are merged into one single updating process to evade the large storage requirement. The circuit is used as a hardware accelerator of a softcore processor in a system-on-programmable chip for physical performance measurement. Experimental results show that the proposed solution is an effective alternative for cluster analysis with low computational cost and high performance.

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Periodical:

Applied Mechanics and Materials (Volumes 284-287)

Pages:

3079-3086

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.284-287.3079

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Online since:

January 2013

Authors:

Chien Min Ou, Wen Jyi Hwang, Ssu Min Yang

Keywords:

Field-Programmable Gate Array (FPGA), Fuzzy Clustering, Reconfigurable Computing, System on Chip (SoC), VLSI

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