Design on Embedded Processor with Configurable Divider

Abstract:

By analyzing Cortex-M3 Instruction Set and AHB Bus protocol, a Cortex-M3 Instruction Set compatible 32-bit RISC embedded microprocessor with built-in an optimized 5+2-stage pipeline was realized in this paper. The performance of the 32-bit RISC processor is optimized by deepening pipeline and optimizing functional modules compared with Cortex-M3. According to division instructions, a configurable hardware divider in different realization ways was realized for different applications. The design of the system architecture was completed using Verilog hardware description language (Verilog HDL) and Top-down methodology. The logic function was corrected by VCS simulation FPGA verification. Design Compiler synthesis result shows that, the maximal dominant frequency of the RISC embedded microprocessor could be up to 95MHz with the 0.18um CMOS process of SMIC, and is improved by 31.94% compared with STM32 Cortex-M3 (72MHz).

• Periodical: Applied Mechanics and Materials (Volumes 336-338)
• Pages: 1504-1509
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.336-338.1504
• Online since: July 2013
• Authors: Song Zhang, Yi Zhang, Lian Fa Bai, Wen Jiang Li
• Keywords: 5-Stage Pipeline, Configurable Divider, Reduced Instruction Set Computer (RISC) Microprocessor, Top-Down Methodology, Verilog Hardware Description Language

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