Design for Realizing Arbitrary Fractional Divider Based on FPGA which Duty Cycle is up to 50%

Song Wei Zhang; Cheng Zhao

doi:10.4028/www.scientific.net/AMM.347-350.1653

Paper Titles

Study on Transient Thermal Resistance of Microwave Pulse Power Device
p.1630

Design of Web Based Secure Embedded System in C
p.1635

Simulation, Fabrication and Characterization of 4500V 4H-SiC Normally-Off VJFET
p.1641

An Improved Channel Estimation Method in OFDM System
p.1646

Design for Realizing Arbitrary Fractional Divider Based on FPGA which Duty Cycle is up to 50%
p.1653

Design of Embedded System-Based CAPTCHA in C
p.1658

Fabrication of L Band 4H-SiC SIT Devices
p.1663

Research on Real-Time Moving Method of Electronic Equipment Virtual Maintenance Prototyping Model
p.1668

A Submicron InGaAs/InP Double Heterojunction Bipolar Transistor with Ft and Fmax of 280GHz
p.1673

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 347-350Design for Realizing Arbitrary Fractional Divider...

Design for Realizing Arbitrary Fractional Divider Based on FPGA which Duty Cycle is up to 50%

Abstract:

This paper proposes a novel method for realizing arbitrary fractional divider based on FPGA. Analyzing the limitations of the existing frequency-divided methods, a new model which consists of two-level dividers is put forward. An arbitrary frequency-divided clock output can be obtained by this method approaching 50% of duty cycle. When the division factor is greater than 128, the duty cycle can be very close to 50% of the clock output. This method is proved to be feasible on the FPGA chip of ALTERA.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volumes 347-350)

Pages:

1653-1657

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.347-350.1653

Citation:

Cite this paper

Online since:

August 2013

Authors:

Song Wei Zhang, Cheng Zhao

Keywords:

Duty Cycle, Field-Programmable Gate Array (FPGA), Fractional Divider

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

References

[1] ZHANG Qi-hui, Wu Chao, Wang Er-ping, et. ptimization Design of Frequency Dividers Based on Verilog HDL, Journal of Henan Univerisity(Natural Science Edition), vol. 37(4) , Aug. 2007，pp.343-346.

Google Scholar

[2] WANG Jian-rong, LI Zhu, TANG Hong-ming. New Parameterized Design of decimal Fractional Frequecy Divider Based on FPGA, Journal of Taiyuan Univerisity of Science and Techonolgy, vol. 28(3), Jun. 2007, pp.191-194.

Google Scholar

[3] YUAN Quan, CHEN Xiao Long, WANG Jia Li. Method of realizing the decimal frequency diveder based on FPGA, Electronic Technology Applications, vol. 36(11), Nov. 2010, pp.99-101.

Google Scholar

[4] LIU Yahai, LIN Zhenghui. Realization of Decimal Frequency Divider Based on FPGA[J], Modern Electronics Technique, vol. 36(11), Nov. 2010, pp.99-101.

Google Scholar

[5] GU Liangling, YANG Yongming, GUO Qiaohui. Parametric Design of FPGA-based half-integer and integer divider, Electronic Devices, vol. 28( 2), Feb. 2005, pp.404-406.

Google Scholar

[6] MAO Weiyong, QI Zhongyang, WANG Lan. Design for decimal frequency divider based on FPGA[J]. Joural of GuiLin College of Aerospace Technology, vol. 53 (1), Jan. 2009, pp.30-32.

Google Scholar

[7] ZHANG Jianyu, Sun Chengshou, LAI Jinmei. Design and Realization of synthesizer programmable divider for 2. 4 GHz frequency , Journal of Fudan University: Natural Science Edition, vol. 44 (1), Jan. 2005, p.139.

DOI: 10.1109/aspdac.2005.1466608

Google Scholar

[8] ZHOU Dongcheng, WANG Yongbin, ZHENG Yaping. Design of Fractional-N Frequency Synthesizer based on FPGA, Electronic Measurement Technology, vol. 29(3), Mar. 2006, p.79 – 93.

Google Scholar