Simulation, Fabrication and Characterization of 4500V 4H-SiC Normally-Off VJFET

Run Hua Huang; Gang Chen; Song Bai; Rui Li; Yun Li; Yong Hong  Tao

doi:10.4028/www.scientific.net/AMM.347-350.1641

Paper Titles

Direct Extraction Method of InP HBT Small-Signal Model
p.1621

Realization of CAN Based on Automotive Open System Architecture
p.1625

Study on Transient Thermal Resistance of Microwave Pulse Power Device
p.1630

Design of Web Based Secure Embedded System in C
p.1635

Simulation, Fabrication and Characterization of 4500V 4H-SiC Normally-Off VJFET
p.1641

An Improved Channel Estimation Method in OFDM System
p.1646

Design for Realizing Arbitrary Fractional Divider Based on FPGA which Duty Cycle is up to 50%
p.1653

Design of Embedded System-Based CAPTCHA in C
p.1658

Fabrication of L Band 4H-SiC SIT Devices
p.1663

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 347-350Simulation, Fabrication and Characterization of...

Simulation, Fabrication and Characterization of 4500V 4H-SiC Normally-Off VJFET

Abstract:

Simulation, Fabrication and characteristics of high voltage, normally-off JFETs in 4H-SiC are presented. The devices were built on ND= 1.01015 cm-3 doped 50μm thick n-type epilayer grown on a n+ 4H-SiC. Parameters of edge termination have been optimized by simulations. Its blocking voltage exceeds 4500V at gate bias VG = -6V and forward drain current is in excess of 3A at gate bias VG = 3V and drain bias VD = 5V corresponding a current density of 80A/cm2.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volumes 347-350)

Pages:

1641-1645

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.347-350.1641

Citation:

Cite this paper

Online since:

August 2013

Authors:

Run Hua Huang, Gang Chen, Song Bai, Rui Li, Yun Li, Yong Hong Tao

Keywords:

4H-SiC, Implant, Ohmic, Trench, VJFET

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

References

[1] Rueschenschmidt K, T reu M, Rupp R, et al. SiC JFET: currently the best solution for an unipolar SiC high power switch. Material Science Forum, 2009, 600-603: 901-906.

DOI: 10.4028/www.scientific.net/msf.600-603.901

Google Scholar

[2] J. Zhang J.H. Zhao, P. Alexandrov and T. Burke. Demonstration of ﬁrst 9. 2 kV 4H-SiCbipolar junction transistor. ELECTRONICS LETTERS 14th October 2004 Vol. 40 No. 21.

DOI: 10.1049/el:20046223

Google Scholar

[3] M. Bouarroudj-Berkani, D. Othman, S. Lefebvre,S. Moumen, Z. Khatir, T. Ben Sallah. Ageing of SiC JFET transistors under repetitive current limitation conditions. Microelectronics Reliability. 21 August 2010 doi: 10. 1016/j. microrel. 2010. 07. 035.

DOI: 10.1016/j.microrel.2010.07.035

Google Scholar

[4] NI Weijiang, LI Yuzhu, LI Zheyang, et al. 1200V Normally-on 4H-SiC VJFET. RESEARCH & PROGRESS OF SSE, Vol. 31, No. 2, Apr., 2011, 103-106.

Google Scholar

[5] Gang Chen, Xiaofeng Song, Song Bai，et al. 5A 1300V Trenched and Implanted 4H-SiC vertical JFET. Applied Mechanics and Materials, 2012; 229-231: 824-827.

DOI: 10.4028/www.scientific.net/amm.229-231.824

Google Scholar

[6] R. Perez, D. Tournier, A. Perez-Tomas, P. Godignon, N. Mestres, and J. Millan. Planar edge termination design and technology considerations for 1. 7-kV 4H-SiC PiN diodes. Electron Devices, IEEE Transactions on, 52(10) : 2309 – 2316, oct. (2005).

DOI: 10.1109/ted.2005.856805

Google Scholar

[7] V. Veliadis, M. Snook, T. McNutt, H. Hearne, P. Potyraj, Aivars Lelis, and C. Scozzie, A 2055-V (at 0. 7 mA/cm2) 24-A (at 706 W/cm2) Normally On 4H-SiC JFET With 6. 8-mm2 Active Area and locking-Voltage Capability Reaching the Material Limit. IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 12, DECEMBER 2008, 1325-1327.

DOI: 10.1109/led.2008.2006766

Google Scholar