Design of Broadband, High-Speed Dual-Modulus Prescaler for Multi-Mode PLL Frequency Synthesizer

Xue Fei Jiang; Xiang Ning Fan

doi:10.4028/www.scientific.net/AMM.364.439

Paper Titles

Remote Multi-Processor Updating System Based on In-System Programming and CAN-Bus
p.419

Monitoring System of Greenhouse Based on GPRS Wireless Communication Technology
p.424

Design of a 0.7~3.8GHz Wideband Power Amplifier in 0.18-μm CMOS Process
p.429

A Wideband 9 GHz LC-VCO with Tail Current Source Array in 0.18-μm RF CMOS Process
p.434

Design of Broadband, High-Speed Dual-Modulus Prescaler for Multi-Mode PLL Frequency Synthesizer
p.439

A 1V Low Voltage 4GHz Phase-Switching Dual-Modulus Prescaler in 0.18μm CMOS
p.444

The Simulation and Application in Eliminating Noise of Adaptive Filter
p.449

Design and Preparation Method of Fiber Optoacoustic Effect Device Used for Artificial Optical Cochlea
p.453

Design of an Active-Gm-RC Reconfigurable Filter for the Multi-Mode Receiver
p.458

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 364Design of Broadband, High-Speed Dual-Modulus...

Design of Broadband, High-Speed Dual-Modulus Prescaler for Multi-Mode PLL Frequency Synthesizer

Abstract:

A architecture of multi-mode PLL frequency synthesizer one can meet a variety of communication standards is presented in this paper, which can provide each mode with the required frequency, while reducing the system's hardware cost. Optimized broadband high-speed dual-mode prescaler (DMP)'s internal structure, the principle of circuit design and its layout is introduced. The DMP is produced by 0.18μm CMOS technology. The post simulation results show that with the 1.8V power, the DMP's operating frequency range is 0.4 ~ 9.6GHz, the power consumption is 7.6mA.

You might also be interested in these eBooks

Mechanical Automation and Materials Engineering

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volume 364)

Pages:

439-443

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.364.439

Citation:

Cite this paper

Online since:

August 2013

Authors:

Xue Fei Jiang, Xiang Ning Fan

Keywords:

Broadband, Dual-Modulus Prescaler, High-Speed, Multi-Mode PLL Frequency Synthesizer

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

References

[1] M. Brandolini, P. Rossi, D. Manstretta and F. Svelto. Toward Multistandard Mobile Terminals-Fully Integrated Receivers Requirements and Architectures[J]. IEEE Trans. Microwave Theory and Techniques, 53(3): 1026-1038, March (2005).

DOI: 10.1109/tmtt.2005.843505

Google Scholar

[2] Jaewook Shin, Hyunchol Shin. A 1. 9–3. 8 GHz ΔΣ Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency[J]. IEEE Journal of Solid-State Circuits, 47(3): 665-675, (2012).

DOI: 10.1109/jssc.2011.2179733

Google Scholar

[3] U. Singh and M. Green. Dynamics of High-Frequency CMOS Divider[C]. IEEE pro. ISCAS, 5: 26-29, May (2002).

Google Scholar

[4] Foroudi N, Kwasniewski T. A CMOS High Speed Dual-Modulus Frequency Divider for RF Frequency Synthesis[J]. IEEE Journal of Solid-state circuits, 30(2): 93-100, (1995).

DOI: 10.1109/4.341735

Google Scholar

[5] Chang B, Park J, Kin W．A 1. 2 GHz CMOS Dual Modulus Prescaler Using Dynamic D-Type FIip-Flop[J]. IEEE Jounal of Solid-state Circuits, 1(5): 749 - 752, (1996).

DOI: 10.1109/4.509860

Google Scholar

[6] Wen-Rong Yang, Jia-Lin Lao, Fen Ran and Jian Wang. A 2. 5 GHz CMOS Dual-modulus Prescaler for RF Frequency Synthesizer[C]. IEEE Solid-State and Integrated Circuits Technology, 2: 1547 - 1550, (2004).

DOI: 10.1109/icsict.2004.1436910

Google Scholar

[7] J. Yuan and C. Svensson. High Speed CMOS Circuit Technique[J]. IEEE Jounal of Solid-state Circuits, 24(1): 62 - 70, (1989).

DOI: 10.1109/4.16303

Google Scholar