Reduction of Glitch Interference in FPGA Design

Guo Hai Xiong; Xin Yun Liu

doi:10.4028/www.scientific.net/AMM.385-386.1268

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 385-386Reduction of Glitch Interference in FPGA Design

Reduction of Glitch Interference in FPGA Design

Abstract:

The cause of generating glitch during the use of FPGA for designing electronic system is discussed. Signals have certain delay when passing through the FPGA device, thereby making the combinational logic output to generate sequencing, and some incorrect glitch signals could be generated, which affect the stability of the circuit. The article proposes that methods of gray code, delay method and synchronous circuit can be adopted to reduce glitch interference in FPGA design from the aspects of software and hardware, the above method is comprehensively used in designing electronic design to ensure that the system is not affected by glitch, thereby improving the reliability of the system.

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Periodical:

Applied Mechanics and Materials (Volumes 385-386)

Pages:

1268-1271

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.385-386.1268

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Online since:

August 2013

Authors:

Guo Hai Xiong, Xin Yun Liu

Keywords:

Glitch, Grad Code, Interference, Synchronous Circuit, Time Delay Method

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References

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