Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

Abstract:

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

• Periodical: Applied Mechanics and Materials (Volumes 385-386)
• Pages: 1278-1281
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.385-386.1278
• Online since: August 2013
• Authors: Zheng Fei Hu, Ying Mei Chen, Shao Jia Xue
• Keywords: Bang-Bang Phase Detector (PD), CDR, Quadrature Voltage-Controlled Oscillator (QVCO)

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