Design of Encoder and Decoder for Q-Ary LDPC Codes Based on FPGA

Zhong Xun Wang; Peng Xiang Wang

doi:10.4028/www.scientific.net/AMM.385-386.1282

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 385-386Design of Encoder and Decoder for Q-Ary LDPC Codes...

Design of Encoder and Decoder for Q-Ary LDPC Codes Based on FPGA

Abstract:

The scheme of FPGA hardware implementation based on the RA structure of encoder for q-ary LDPC codes as well as the Max-log-BP decoding are designed emphasisly. Form the performance, speed, and resource consumption situation of coder and decoder, this scheme based on FPGA can meet the requirements of the most of communication systems.

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Periodical:

Applied Mechanics and Materials (Volumes 385-386)

Pages:

1282-1287

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.385-386.1282

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Online since:

August 2013

Authors:

Zhong Xun Wang, Peng Xiang Wang

Keywords:

Field-Programmable Gate Array (FPGA), Hardware Implementation, Q-Ary LDPC Codes, Repeat Accumulate (RA) Codes

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References

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