A 4-Bit 5 GS/s Current Steering DAC Integrated Circuit

Weng Yuan Li; Teng Xiao Jiang

doi:10.4028/www.scientific.net/AMM.513-517.4555

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 513-517A 4-Bit 5 GS/s Current Steering DAC Integrated...

A 4-Bit 5 GS/s Current Steering DAC Integrated Circuit

Abstract:

In order to satisfy the higher and higher transmission rate and broadband requirement of modern communication, a 4-bit 5 GS/s digital-to-analog converter (DAC) integrated circuit is presented. The DAC circuit is based on current steering architecture and segmented with a 4 bit unary. The circuit is designed and analyzed in TSMC 0.18 μm CMOS technology. The chip size is 0.675 mm 0.525 mm. Simulation results show that the maximum integral nonlinearity (INL) is 0.15 LSB. The DAC can achieve a spurious-free dynamic range (SFDR) of 22.76 dB under a clock frequency of 5 GHz with an input signal frequency of 250 MHz, while the power consumption is 11.6 mW.

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Periodical:

Applied Mechanics and Materials (Volumes 513-517)

Pages:

4555-4558

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.513-517.4555

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Online since:

February 2014

Authors:

Weng Yuan Li*, Teng Xiao Jiang

Keywords:

CMOS, Current Steering, Digital-to-Analog Converter (DAC), Integrated Circuit, Ultra-High-Speed

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