Implementation and Application of Short-Time Fourier Transform on a New High Speed FPGA

Abstract:

FPGA structures are common designed in Serial structure and Parallel structure. As the most efficient one, Parallel structure also could be divided into whole-parallel and half-parallel which we called pipe-line structure. Whole Parallel structure FPGA take a great advantage on speed but consuming enormous resources. Moreover, FFT cannot give enough details on Time-frequency domain. In order to avoid these disadvantages, proposed STFT processer plan on FPGA. Based on the research on algorithms STFT, we gave an improved pipeline structure FPGA design. Then this design implied high speed STFT which take both speed and precision into count on FPGA. At the last of this paper, we conducted signal test. In this step , any signals were all collected from actual work condition. And then verify the feasibility of the program through simulation and actual signal test.

• Periodical: Applied Mechanics and Materials (Volumes 556-562)
• Pages: 1838-1841
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.556-562.1838
• Online since: May 2014
• Authors: Gui Gui, Li Peng Qiu*
• Keywords: Diagnosis, FPGA, Fully Parallel Architecture, STFT

References

[1] Wang xudong, Liu yu. Journal of Nanjing University of Aeronautics & Astronautics, 2006(38-1), 96-100.

[2] Xie yingke, Fu bo. Jounal of computer research and development v01. 41. No. 6 June (2004).

[3] Xia mingyun, Jiang tao. Implementation of a Fast Fourier Transform Algorithm Based on FPGA. [J]. Communications Technology, 2012(7-45), 113-115.

[4] Wang zhen, Sun lan, Yang yang. Implementation and Application of Shory-time Fourier Transform Based on FPGA. [J]. Noise and Vibration Control, 2012(10-5), 154-158.

[5] Baese, Digital Signal Processing with Field Programmable Gate Arrays[M], Third Edition.