Design and Verification of a Scalable Enhanced High Performance DMA Architecture for Complex SoC

Abstract:

As the demand of higher image quality and greater processing capabilities are growing, obtaining higher data bandwidth for on-chip processing is becoming a more and more important issue. DMA (Direct Memory Access) component, as the key element in stream processing SoC (System on Chip) [1], should be deeply researched and designed to satisfy the high data bandwidth requirement of processing units. In this paper, we introduce a scalable high-performance DMA architecture for complex SoC to satisfy rigorous high sustained bandwidth and versatile functionality requirements. Several techniques and structures are proposed in this paper. A state-in-art verification environment is built for our design to fully verify its functionality. At the end of the paper, the tape-out results are provided. The whole implementation has been silicon proven to be functional and efficient.

• Periodical: Applied Mechanics and Materials (Volumes 556-562)
• Pages: 4303-4308
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.556-562.4303
• Online since: May 2014
• Authors: Hua Long Zhao*
• Keywords: DMA, OVM, Systemverilog Verification, TPRAM, TR Pipelining

References

[1] B. Khailany et al., Imagine: Media processing with streams, IEEE Micro, 21(2): 35–46, (2001).

[2] D. Comisky, S. Agarwala, and C. Fuoco, A scalable high performance DMA architecture for DSP applications, in Proc. of International Conference Computer Design, IEEE, Austin, TX, pp.414-419, Sept. (2000).

DOI: 10.1109/iccd.2000.878317

[3] Synopsys, DesignWare DW AHB DMAC Databook, December (2006).

[4] ARM, PrimeCell Advanced DMA Controller (PL330) Technical Reference Manual, May 21, (2008).

[5] Chia-Hao Yu et al. An efficient DMA controller for multimedia application in MPU based SoC, ICME2007.

[6] OVM Organization, OVM User Guide, Version 2. 1. 1, March (2010).