Design of a Reconfigurable Coprocessor for Double Precision Floating Point Matrix Algorithms

Abstract:

Double precision floating point matrix operations are wildly used in a variety of engineering and scientific computing applications. However, it’s inefficient to achieve these operations using software approaches on general purpose processors. In order to reduce the processing time and satisfy the real-time demand, a reconfigurable coprocessor for double precision floating point matrix algorithms is proposed in this paper. The coprocessor is embedded in a Multi-Processor System on Chip (MPSoC), cooperates with an ARM core and a DSP core for high-performance control and calculation. One algorithm in GPS applications is taken for example to illustrate the efficiency of the coprocessor proposed in this paper. The experiment result shows that the coprocessor can achieve speedup a factor of 50 for the quaternion algorithm of attitude solution in inertial navigation application compare with software execution time of a TI C6713 DSP. The coprocessor is implemented in SMIC 0.13μm CMOS technology, the synthesis time delay is 9.75ns, and the power consumption is 63.69 mW when it works at 100MHz.

• Periodical: Applied Mechanics and Materials (Volumes 58-60)
• Pages: 1037-1042
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.58-60.1037
• Online since: June 2011
• Authors: Sheng Long Li, Zhao Lin Li, Qing Wei Zheng
• Keywords: Double Precision Floating Point Matrix Algorithm, Multi-Processor System on Chip, Quaternion Algorithm, Reconfigurable Coprocessor

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