The Design and Implement of SSD Chip with Multi-Bus and 8 Channels

Abstract:

As networks and the development of information technology, the traditional machinery hard in some areas has been unable to satisfy the speed and performance requirements, and appeared SSD（solid state disk）. This article describes the design of a high-performance SSD control chip,the SSD control chip intergrate internal ARM7 processor, by AHB bus to rapid implement the dma data transmission, the interface with nandflash adopted eight, which can achieve on the parallel operation and improve nandflash interface speed. With the host interface uses sata2.Firmware use of the FTL algorithms, including and of the operation of the mapping. A balanced mix of wear and tear, a bad piece of management and garbage collection, and more efficient to access to SSD, improved ssd life. That the SSD chip for reading speed 200MB/S, the maximum writing speed is 140MB/s.

• Periodical: Applied Mechanics and Materials (Volumes 58-60)
• Pages: 2592-2596
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.58-60.2592
• Online since: June 2011
• Authors: Zhi Lou Yu, Ji Hua, Li Feng
• Keywords: AHB Bus, ARM, CRC, ECC, Flash Translation Layer (FTL), Garbage Collection, NFC(Nand Flash Controller);, Solid State Disk (SSD), Wear Balance

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